From 8a38d9f53b494fe8a563a52435279368046aeecb Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Fri, 21 May 2021 16:09:00 +0800 Subject: [PATCH] arm64: dts: rockchip: change naneng combphy ref clock to 100mhz for rk3568 When using 24MHz reference clock, some devices can't identify the SATA PM chip, And the signal quality is not as good as 100MHz. so change the reference clock to 100MHz. Signed-off-by: Yifeng Zhao Change-Id: If7d951a0b77d503f9faf1c1f88c78a9e07471e47 --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index aebc94dd4e0c..ecd76ae82dcf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -3086,7 +3086,7 @@ combphy0_us: phy@fe820000 { <&cru PCLK_PIPE>; clock-names = "refclk", "apbclk", "pipe_clk"; assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; - assigned-clock-rates = <24000000>; + assigned-clock-rates = <100000000>; resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&pipegrf>; @@ -3102,7 +3102,7 @@ combphy1_usq: phy@fe830000 { <&cru PCLK_PIPE>; clock-names = "refclk", "apbclk", "pipe_clk"; assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; - assigned-clock-rates = <24000000>; + assigned-clock-rates = <100000000>; resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; reset-names = "combphy-apb", "combphy"; rockchip,pipe-grf = <&pipegrf>;