From 0085a33a25cc534838f801d697f87725e835743c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 30 Nov 2020 15:09:22 +0530 Subject: [PATCH 001/100] arm64: dts: qcom: sm8250: Add support for LLCC block Add support for Last Level Cache Controller (LLCC) in SM8250 SoC. This LLCC is used to provide common cache memory pool for the cores in the SM8250 SoC thereby minimizing the percore caches. Reviewed-by: Sai Prakash Ranjan Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20201130093924.45057-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..118b6bb29ebc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1758,6 +1758,12 @@ usb_1_dwc3: dwc3@a600000 { }; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8250-llcc"; + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + usb_2: usb@a8f8800 { compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>; From 221f0ef37f5529fe35110651452f9c05dcb7bf8e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 27 Nov 2020 12:26:46 +0300 Subject: [PATCH 002/100] arm64: dts: sm8250-mtp: enable USB host nodes Enable both USB host controller, hsphy and qmpphy nodes on sm8250. Add missing pm8150 ldo18 definition (used by USB qmp phys). Both controllers are locked to host mode: dual role on first controller is not enabled. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201127092646.122663-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index dea00f19711d..3aac17604ff0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -186,6 +186,13 @@ vreg_l17a_3p0: ldo17 { regulator-max-microvolt = <3008000>; regulator-initial-mode = ; }; + + vreg_l18a_0p9: ldo18 { + regulator-name = "vreg_l18a_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; }; pm8150l-rpmh-regulators { @@ -426,3 +433,49 @@ &ufs_mem_phy { vdda-pll-supply = <&vreg_l9a_1p2>; vdda-pll-max-microamp = <19000>; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5a_0p875>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l2a_3p1>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p9>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5a_0p875>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l2a_3p1>; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p9>; +}; From 7c1dffd471b14dbf738268c7c0b3e43b362fa5db Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Dec 2020 17:20:59 +0300 Subject: [PATCH 003/100] arm64: dts: qcom: sm8250.dtsi: add display system nodes Add device tree nodes for mdss, mdp, dsi0/1. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201203142105.841666-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 302 ++++++++++++++++++++++++++- 1 file changed, 295 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 118b6bb29ebc..827197f83f4f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4,10 +4,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -1254,14 +1256,8 @@ tcsr_mutex: hwlock@1f40000 { }; gpu: gpu@3d00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ compatible = "qcom,adreno-650.2", - "qcom,adreno", - "amd,imageon"; + "qcom,adreno"; #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>; @@ -1809,6 +1805,298 @@ usb_2_dwc3: dwc3@a800000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sdm845-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>, + <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "notused", "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <460000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sdm845-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8250-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk", + "dptx2_phy_pll_link_clk", + "dptx2_phy_pll_vco_div_clk", + "edp_phy_pll_link_clk", + "edp_phy_pll_vco_div_clk", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; From 46967bb61a20f6eb7417193e494a62ba5b0f760f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Dec 2020 17:21:00 +0300 Subject: [PATCH 004/100] arm64: dts: qrb5165-rb5: add mdss/mdp/dsi nodes Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201203142105.841666-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index ce22d4fa383e..ce9d98e2d856 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -406,6 +406,30 @@ vreg_s8c_1p3: smps8 { }; }; +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l9a_1p2>; + +#if 0 + qcom,dual-dsi-mode; + qcom,master-dsi; +#endif + + ports { + port@1 { + endpoint { + //remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l5a_0p88>; +}; + /* LS-I2C0 */ &i2c4 { status = "okay"; @@ -420,6 +444,14 @@ &i2c15 { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pm8150_gpios { gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; gpio-line-names = From 0b2033dcf4afa399addacdf2f24600894fb947d7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Dec 2020 17:21:01 +0300 Subject: [PATCH 005/100] arm64: dts: qcom: qrb5165-rb5: add gpu/zap-shader node Add firmware configuration for Adreno zap shader on qrb5165-rb5. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201203142105.841666-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index ce9d98e2d856..22c1953f4e63 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -430,6 +430,13 @@ &dsi0_phy { vdds-supply = <&vreg_l5a_0p88>; }; +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sm8250/a650_zap.mbn"; + }; +}; + /* LS-I2C0 */ &i2c4 { status = "okay"; From 9e301a547a7eadab8e6d4089eac9e6a123d18d23 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Dec 2020 17:21:02 +0300 Subject: [PATCH 006/100] arm64: dts: qcom: sm8250-mtp: add gpu/zap-shader node Add firmware configuration for Adreno zap shader on sm8250-mtp. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201203142105.841666-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 3aac17604ff0..767a2e446248 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -365,6 +365,13 @@ &cdsp { firmware-name = "qcom/sm8250/cdsp.mbn"; }; +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sm8250/a650_zap.mbn"; + }; +}; + &i2c1 { status = "okay"; clock-frequency = <1000000>; From 04c8e3f7e9e9675a01182dea2a4ebe2fe26ad706 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Dec 2020 17:21:03 +0300 Subject: [PATCH 007/100] arm64: dts: qcom: qrb5165-rb5: correct vdc_3v3 regulator vdc_3v3 regulator is sourced from 12V, but it is controlled by l11c regulator, so set it as vin for vdc_3v3. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201203142105.841666-6-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 22c1953f4e63..94d95dff48c4 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -87,7 +87,7 @@ vbat_som: vbat-som-regulator { vdc_3v3: vdc-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "VDC_3V3"; - vin-supply = <&dc12v>; + vin-supply = <&vreg_l11c_3p3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; From d004c631ea4e1327cf04316ff444e7e078e00d77 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Dec 2020 17:21:04 +0300 Subject: [PATCH 008/100] arm64: dts: qcom: qrb5165-rb5: add lt9611 HDMI bridge Add device tree node for the lontium lt9611ux DSI-HDMI bridge. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201203142105.841666-7-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 97 +++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 94d95dff48c4..1ade62d98f98 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -40,6 +40,17 @@ dc12v: dc12v-regulator { regulator-always-on; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -66,6 +77,26 @@ bt { }; + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + lt9611_3v3: lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vdc_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; @@ -418,7 +449,7 @@ &dsi0 { ports { port@1 { endpoint { - //remote-endpoint = <<9611_a>; + remote-endpoint = <<9611_a>; data-lanes = <0 1 2 3>; }; }; @@ -444,6 +475,55 @@ &i2c4 { &i2c5 { status = "okay"; + clock-frequency = <400000>; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + +#if 0 + port@1 { + reg = <1>; + + lt9611_b: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; +#endif + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + }; + }; }; /* LS-I2C1 */ @@ -504,6 +584,15 @@ &pm8150l_gpios { "PM_GPIO-B", "NC", "PM3003A_MODE"; + + lt9611_rst_pin: lt9611-rst-pin { + pins = "gpio5"; + function = "normal"; + + output-high; + input-disable; + power-source = <0>; + }; }; &pm8150_rtc { @@ -735,6 +824,12 @@ &tlmm { "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; + lt9611_irq_pin: lt9611-irq { + pins = "gpio63"; + function = "gpio"; + bias-disable; + }; + sdc2_default_state: sdc2-default { clk { pins = "sdc2_clk"; From 3f2094dfbe691d3d31b8a478c83495989773e390 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Dec 2020 17:21:05 +0300 Subject: [PATCH 009/100] arm64: dts: qcom: sm8250: power up dispcc on sm8250 by MMCX regulator Add regulator controlling MMCX power domain to be used by display clock controller on SM8250. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201203142105.841666-8-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 827197f83f4f..ce571796561c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -216,6 +216,13 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + mmcx_reg: mmcx-reg { + compatible = "regulator-fixed-domain"; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + regulator-name = "MMCX"; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2064,6 +2071,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x20000>; + mmcx-supply = <&mmcx_reg>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>, From 63e10791ccab664abc031b7fad07674fdae2d829 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 2 Dec 2020 18:07:36 +0000 Subject: [PATCH 010/100] arm64: dts: qcom: sm8250: add apr and its services Add apr node and its associated services required for audio on RB5. Signed-off-by: Srinivas Kandagatla Tested-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201202180741.16386-2-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 56 ++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index ce571796561c..3aca8d0af97c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -13,7 +13,9 @@ #include #include #include +#include #include +#include #include / { @@ -2922,6 +2924,60 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "lpass"; qcom,remote-pid = <2>; + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,apr-domain = ; + #address-cells = <1>; + #size-cells = <0>; + + apr-service@3 { + reg = ; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: apr-service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: cc { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: apr-service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x1801 0x0>; + }; + }; + + q6adm: apr-service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; From 793bbd2db7e35a9dbf006e81a8373cd1c333ae53 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 2 Dec 2020 18:07:37 +0000 Subject: [PATCH 011/100] arm64: dts: qcom: sm8250: add audio clock controllers Add audiocc and aoncc clock controller nodes required for audio on RB5. Signed-off-by: Srinivas Kandagatla Tested-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201202180741.16386-3-srinivas.kandagatla@linaro.org [bjorn: Dropped includes for now] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 3aca8d0af97c..98d58943cd05 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1264,6 +1264,26 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + audiocc: clock-controller@3300000 { + compatible = "qcom,sm8250-lpass-audiocc"; + reg = <0 0x03300000 0 0x30000>; + #clock-cells = <1>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio", "bus"; + }; + + aoncc: clock-controller@3380000 { + compatible = "qcom,sm8250-lpass-aoncc"; + reg = <0 0x03380000 0 0x40000>; + #clock-cells = <1>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio", "bus"; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-650.2", "qcom,adreno"; From 3160c1b894d9cf5373457f260d4660d6269204ae Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 2 Dec 2020 18:07:38 +0000 Subject: [PATCH 012/100] arm64: dts: qcom: sm8250: add lpass lpi pin controller node Add LPASS LPI pinctrl node required for Audio functionality on RB5. Signed-off-by: Srinivas Kandagatla Tested-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201202180741.16386-4-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 84 ++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 98d58943cd05..7badccba186b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1284,6 +1284,90 @@ aoncc: clock-controller@3380000 { clock-names = "core", "audio", "bus"; }; + lpass_tlmm: pinctrl@33c0000{ + compatible = "qcom,sm8250-lpass-lpi-pinctrl"; + reg = <0 0x033c0000 0x0 0x20000>, + <0 0x03550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 14>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + wsa_swr_active: wsa-swr-active-pins { + clk { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + + }; + }; + + wsa_swr_sleep: wsa-swr-sleep-pins { + clk { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + input-enable; + bias-pull-down; + }; + + data { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + input-enable; + bias-pull-down; + + }; + }; + + dmic01_active: dmic01-active-pins { + clk { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + data { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic01_sleep: dmic01-sleep-pins { + clk { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + data { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-650.2", "qcom,adreno"; From 768270ca57f6a495c9c1d81a1b01ab5ad604b321 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 2 Dec 2020 18:07:39 +0000 Subject: [PATCH 013/100] arm64: dts: qcom: sm8250: add wsa and va codec macros Add support for WSA and VA codec macros along with WSA soundwire controller required for getting audio on RB5. Signed-off-by: Srinivas Kandagatla Tested-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201202180741.16386-5-srinivas.kandagatla@linaro.org [bjorn: Replaced LPASS_CDC clock defines with constants] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 56 ++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7badccba186b..ad0a0a887cc8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1264,6 +1264,47 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + wsamacro: codec@3240000 { + compatible = "qcom,sm8250-lpass-wsa-macro"; + reg = <0 0x03240000 0 0x1000>; + clocks = <&audiocc 1>, + <&audiocc 0>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&aoncc 0>, + <&vamacro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&wsa_swr_active>; + }; + + swr0: soundwire-controller@3250000 { + reg = <0 0x03250000 0 0x2000>; + compatible = "qcom,soundwire-v1.5.1"; + interrupts = ; + clocks = <&wsamacro>; + clock-names = "iface"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + audiocc: clock-controller@3300000 { compatible = "qcom,sm8250-lpass-audiocc"; reg = <0 0x03300000 0 0x30000>; @@ -1274,6 +1315,21 @@ audiocc: clock-controller@3300000 { clock-names = "core", "audio", "bus"; }; + vamacro: codec@3370000 { + compatible = "qcom,sm8250-lpass-va-macro"; + reg = <0 0x03370000 0 0x1000>; + clocks = <&aoncc 0>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + + clock-names = "mclk", "macro", "dcodec"; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + aoncc: clock-controller@3380000 { compatible = "qcom,sm8250-lpass-aoncc"; reg = <0 0x03380000 0 0x40000>; From b657d372627091b832f6aa87d8eae92154c77659 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 2 Dec 2020 18:07:40 +0000 Subject: [PATCH 014/100] arm64: dts: qcom: sm8250: add mi2s pinconfs Add primary and tertinary mi2s pinconfs required to get I2S audio. Signed-off-by: Srinivas Kandagatla Tested-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201202180741.16386-6-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index ad0a0a887cc8..ed5386214355 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2344,6 +2344,37 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 180>; wakeup-parent = <&pdc>; + pri_mi2s_active: pri-mi2s-active { + sclk { + pins = "gpio138"; + function = "mi2s0_sck"; + drive-strength = <8>; + bias-disable; + }; + + ws { + pins = "gpio141"; + function = "mi2s0_ws"; + drive-strength = <8>; + output-high; + }; + + data0 { + pins = "gpio139"; + function = "mi2s0_data0"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data1 { + pins = "gpio140"; + function = "mi2s0_data1"; + drive-strength = <8>; + output-high; + }; + }; + qup_i2c0_default: qup-i2c0-default { mux { pins = "gpio28", "gpio29"; @@ -2940,6 +2971,30 @@ mux { function = "qup18"; }; }; + + tert_mi2s_active: tert-mi2s-active { + sck { + pins = "gpio133"; + function = "mi2s2_sck"; + drive-strength = <8>; + bias-disable; + }; + + data0 { + pins = "gpio134"; + function = "mi2s2_data0"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws { + pins = "gpio135"; + function = "mi2s2_ws"; + drive-strength = <8>; + output-high; + }; + }; }; apps_smmu: iommu@15000000 { From 590a135ebdc7053ec81e35be2a517b916c002ef9 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 2 Dec 2020 18:07:41 +0000 Subject: [PATCH 015/100] arm64: dts: qcom: qrb5165-rb5: Add Audio support This patch add support for two WSA881X smart speakers attached via Soundwire and a DMIC0 on the main board. Signed-off-by: Srinivas Kandagatla Tested-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201202180741.16386-7-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 121 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 + 2 files changed, 124 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 1ade62d98f98..477ff91dc460 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "sm8250.dtsi" #include "pm8150.dtsi" #include "pm8150b.dtsi" @@ -151,6 +153,11 @@ vreg_s4a_1p8: vreg-s4a-1p8 { }; }; +&adsp { + status = "okay"; + firmware-name = "qcom/sm8250/adsp.mbn"; +}; + &apps_rsc { pm8009-rpmh-regulators { compatible = "qcom,pm8009-rpmh-regulators"; @@ -611,6 +618,35 @@ &qupv3_id_2 { status = "okay"; }; +&q6afedai { + qi2s@16 { + reg = <16>; + qcom,sd-lines = <0 1 2 3>; + }; +}; + +/* TERT I2S Uses 1 I2S SD Lines for audio on LT9611 HDMI Bridge */ +&q6afedai { + qi2s@20 { + reg = <20>; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + &sdhc_2 { status = "okay"; pinctrl-names = "default"; @@ -625,6 +661,84 @@ &sdhc_2 { no-emmc; }; +&swr0 { + left_spkr: wsa8810-left{ + compatible = "sdw10217211000"; + reg = <0 3>; + powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: wsa8810-right{ + compatible = "sdw10217211000"; + reg = <0 4>; + powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; +}; + +&sound { + compatible = "qcom,qrb5165-rb5-sndcard"; + pinctrl-0 = <&tert_mi2s_active>; + pinctrl-names = "default"; + model = "Qualcomm-RB5-WSA8815-Speakers-DMIC0"; + audio-routing = + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "MM_DL1", "MultiMedia1 Playback", + "MultiMedia3 Capture", "MM_UL3"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + dma-dai-link { + link-name = "WSA Playback"; + cpu { + sound-dai = <&q6afedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + cpu { + sound-dai = <&q6afedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&vamacro 0>; + }; + }; +}; + /* CAN */ &spi0 { status = "okay"; @@ -926,3 +1040,10 @@ &usb_2_qmpphy { vdda-phy-supply = <&vreg_l9a_1p2>; vdda-pll-supply = <&vreg_l18a_0p92>; }; + +&vamacro { + pinctrl-0 = <&dmic01_active>; + pinctrl-names = "default"; + vdd-micb-supply = <&vreg_s4a_1p8>; + qcom,dmic-sample-rate = <600000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index ed5386214355..9af0bb76f24a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1722,6 +1722,9 @@ compute-cb@8 { }; }; + sound: sound { + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8250-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; From 88b57bc335aec493531a75505391d837041ab935 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Dec 2020 22:13:35 +0300 Subject: [PATCH 016/100] arm64: dts: qcom: sm8250: rename smem device node to follow schema Rename 'qcom,smem' to just 'smem' to follow the rest of SoC (and device schema). Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201203191335.927001-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 9af0bb76f24a..6b4cf4426859 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -332,7 +332,7 @@ cdsp_secure_heap: memory@8bf00000 { }; }; - smem: qcom,smem { + smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; From 465b13cc0ac1e792d844117636296c4359e15504 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 4 Dec 2020 10:49:02 -0800 Subject: [PATCH 017/100] arm64: dts: qcom: Fix SD card vqmmc max voltage on sc7180-trogdor It never makes sense to set the IO voltage of the SD card (vqmmc) to a voltage that's higher than the voltage of the card's main power supply (vmmc). The card's main voltage is 2.952V on trogdor, so let's set the max for the IO voltage to the same. NOTE: On Linux, this is pretty much a no-op currently. Linux already makes an effort to match vqmmc with vmmc when running at "3.3" signal voltage, so both before and after this change we end up running vqmmc at 2.904V when talking to non-UHS cards. It still seems cleaner to make it a little more correct, though. Also note: as per above, on Linux right now we end up running vqmmc as 2.904V even though vmmc is 2.952V. This isn't super ideal but shouldn't really hurt. Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20201204104900.1.I0a4ac2c7f4d405431cf95eb7b7c36800660516ec@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 8ed7dd39f6e3..d76200d2b373 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -509,7 +509,7 @@ pp1800_l5c: ldo5 { vddpx_2: ppvar_l6c: ldo6 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3304000>; + regulator-max-microvolt = <2952000>; regulator-initial-mode = ; }; From bd167507d5b6fffe176eae56d9d9c0b3d26b64e6 Mon Sep 17 00:00:00 2001 From: "J.R. Divya Antony" Date: Wed, 9 Dec 2020 20:07:44 +0530 Subject: [PATCH 018/100] arm64: dts: qcom: Add device tree for ASUS Zenfone 2 Laser ASUS Zenfone 2 Laser Z00L is a smartphone based on MSM8916 SoC released on 2015. Add a device tree for Z00L with initial support for: - SDHCI (internal storage) - USB Device Mode - UART - Regulators Reviewed-by: Stephan Gerhold Signed-off-by: J.R. Divya Antony Link: https://lore.kernel.org/r/20201209143743.7383-1-d.antony.jr@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 195 ++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5113fac80b7a..6a4be237f344 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts new file mode 100644 index 000000000000..cee451e59385 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include + +/ { + model = "Asus Zenfone 2 Laser"; + compatible = "asus,z00l", "qcom,msm8916"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&msmgpio 117 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_keys_default: gpio-keys-default { + pins = "gpio107", "gpio117"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + usb_id_default: usb-id-default { + pins = "gpio110"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; From 8d079bf20410aeb2cc714d8781d3a0930f85448f Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Mon, 14 Dec 2020 18:00:04 -0800 Subject: [PATCH 019/100] arm64: dts: qcom: sc7180: Drop pinconf on dp_hot_plug_det We shouldn't put any pinconf here in case someone decides to invert this HPD signal or remove an external pull-down. It's better to leave that to the board pinconf nodes, so drop it here. Reviewed-by: Douglas Anderson Reported-by: Douglas Anderson Cc: Tanmay Shah Fixes: 681a607ad21a ("arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node") Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20201215020004.731239-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 22b832fc62e3..268fa40a1774 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1468,12 +1468,6 @@ pinmux { pins = "gpio117"; function = "dp_hot"; }; - - pinconf { - pins = "gpio117"; - bias-disable; - input-enable; - }; }; qspi_clk: qspi-clk { From 066d21bcf605727814af2a4d44e96ba578f9103d Mon Sep 17 00:00:00 2001 From: Danny Lin Date: Sun, 20 Dec 2020 16:29:05 -0800 Subject: [PATCH 020/100] arm64: dts: qcom: sm8150: Define CPU topology sm8150 has a big.LITTLE CPU setup with DynamIQ, so all cores are within the same CPU cluster and LLC (Last-Level Cache) domain. Define this topology to help the scheduler make decisions. Signed-off-by: Danny Lin Link: https://lore.kernel.org/r/20201221002907.2870059-2-danny@kdrag0n.dev Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 5270bda7418f..d2159b1aa97e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -157,6 +157,42 @@ L2_700: l2-cache { next-level-cache = <&L3_0>; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; }; firmware { From 81188f585d023f6bf403cb1c79e5037dfd5819ff Mon Sep 17 00:00:00 2001 From: Danny Lin Date: Sun, 20 Dec 2020 16:29:06 -0800 Subject: [PATCH 021/100] arm64: dts: qcom: sm8150: Add PSCI idle states Like other Qualcomm SoCs, sm8150 exposes CPU and cluster idle states through PSCI. Define the idle states to save power when the CPU is not in active use. These idle states, latency, and residency values match the downstream 4.14 kernel from Qualcomm as of LA.UM.8.1.r1-15600-sm8150.0. It's worth noting that the CPU has an additional C3 power collapse idle state between WFI and rail power collapse (with PSCI mode 0x40000003), but it is not officially used in downstream kernels due to "thermal throttling issues." Signed-off-by: Danny Lin Link: https://lore.kernel.org/r/20201221002907.2870059-3-danny@kdrag0n.dev Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 50 ++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index d2159b1aa97e..1b10bc80e483 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -47,6 +47,8 @@ CPU0: cpu@0 { compatible = "qcom,kryo485"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -64,6 +66,8 @@ CPU1: cpu@100 { compatible = "qcom,kryo485"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -79,6 +83,8 @@ CPU2: cpu@200 { compatible = "qcom,kryo485"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -93,6 +99,8 @@ CPU3: cpu@300 { compatible = "qcom,kryo485"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -107,6 +115,8 @@ CPU4: cpu@400 { compatible = "qcom,kryo485"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; @@ -121,6 +131,8 @@ CPU5: cpu@500 { compatible = "qcom,kryo485"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; @@ -135,6 +147,8 @@ CPU6: cpu@600 { compatible = "qcom,kryo485"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; @@ -149,6 +163,8 @@ CPU7: cpu@700 { compatible = "qcom,kryo485"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; @@ -193,6 +209,40 @@ core7 { }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <355>; + exit-latency-us = <909>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <241>; + exit-latency-us = <1461>; + min-residency-us = <4488>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x400000F4>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; }; firmware { From 5b2dae72187de25a90f245482281a9ed0ffd268f Mon Sep 17 00:00:00 2001 From: Danny Lin Date: Sun, 20 Dec 2020 16:29:07 -0800 Subject: [PATCH 022/100] arm64: dts: qcom: sm8150: Add CPU capacities and energy model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Power and performance measurements were made using my freqbench [1] benchmark coordinator, which isolates, offlines, and disables the timer tick on test CPUs to maximize accuracy. It uses EEMBC CoreMark [2] as the workload and measures power usage using the PM8150B PMIC's fuel gauge. The energy model dynamic-power-coefficient values were calculated with DPC = µW / MHz / V^2 for each OPP, and averaged across all OPPs within each cluster for the final coefficient. Voltages were obtained from the qcom-cpufreq-hw driver that reads voltages from the OSM LUT programmed into the SoC. Normalized DMIPS/MHz capacity scale values for each CPU were calculated from CoreMarks/MHz (CoreMark iterations per second per MHz), which serves the same purpose. For each CPU, the final capacity-dmips-mhz value is the C/MHz value of its maximum frequency normalized to SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system. An Asus ZenFone 6 device running a downstream Qualcomm 4.14 kernel (LA.UM.8.1.r1-15600-sm8150.0) was used for benchmarks to ensure proper frequency scaling and other low-level controls. Raw benchmark results can be found in the freqbench repository [3]. Below is a human-readable summary: Frequency domains: cpu1 cpu4 cpu7 Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 Baseline power usage: 1400 mW ===== CPU 1 ===== Frequencies: 300 403 499 576 672 768 844 940 1036 1113 1209 1305 1382 1478 1555 1632 1708 1785 300: 1114 3.7 C/MHz 52 mW 11.8 J 21.3 I/mJ 224.4 s 403: 1497 3.7 C/MHz 57 mW 9.5 J 26.2 I/mJ 167.0 s 499: 1854 3.7 C/MHz 73 mW 9.8 J 25.5 I/mJ 134.9 s 576: 2139 3.7 C/MHz 83 mW 9.7 J 25.8 I/mJ 116.9 s 672: 2495 3.7 C/MHz 65 mW 6.5 J 38.6 I/mJ 100.2 s 768: 2852 3.7 C/MHz 72 mW 6.3 J 39.4 I/mJ 87.7 s 844: 3137 3.7 C/MHz 77 mW 6.2 J 40.5 I/mJ 79.7 s 940: 3493 3.7 C/MHz 84 mW 6.0 J 41.8 I/mJ 71.6 s 1036: 3850 3.7 C/MHz 91 mW 5.9 J 42.5 I/mJ 64.9 s 1113: 4135 3.7 C/MHz 96 mW 5.8 J 43.2 I/mJ 60.5 s 1209: 4491 3.7 C/MHz 102 mW 5.7 J 44.2 I/mJ 55.7 s 1305: 4848 3.7 C/MHz 110 mW 5.7 J 44.0 I/mJ 51.6 s 1382: 5133 3.7 C/MHz 114 mW 5.5 J 45.2 I/mJ 48.7 s 1478: 5490 3.7 C/MHz 120 mW 5.5 J 45.7 I/mJ 45.5 s 1555: 5775 3.7 C/MHz 126 mW 5.5 J 45.8 I/mJ 43.3 s 1632: 6060 3.7 C/MHz 131 mW 5.4 J 46.1 I/mJ 41.3 s 1708: 6345 3.7 C/MHz 137 mW 5.4 J 46.3 I/mJ 39.4 s 1785: 6630 3.7 C/MHz 146 mW 5.5 J 45.5 I/mJ 37.7 s ===== CPU 4 ===== Frequencies: 710 825 940 1056 1171 1286 1401 1497 1612 1708 1804 1920 2016 2131 2227 2323 2419 710: 2765 3.9 C/MHz 126 mW 11.4 J 22.0 I/mJ 90.4 s 825: 6432 7.8 C/MHz 206 mW 8.0 J 31.2 I/mJ 38.9 s 940: 7331 7.8 C/MHz 227 mW 7.7 J 32.3 I/mJ 34.1 s 1056: 8227 7.8 C/MHz 249 mW 7.6 J 33.0 I/mJ 30.4 s 1171: 9127 7.8 C/MHz 261 mW 7.2 J 34.9 I/mJ 27.4 s 1286: 10020 7.8 C/MHz 289 mW 7.2 J 34.6 I/mJ 25.0 s 1401: 10918 7.8 C/MHz 311 mW 7.1 J 35.1 I/mJ 22.9 s 1497: 11663 7.8 C/MHz 336 mW 7.2 J 34.7 I/mJ 21.4 s 1612: 12546 7.8 C/MHz 375 mW 7.5 J 33.5 I/mJ 19.9 s 1708: 13320 7.8 C/MHz 398 mW 7.5 J 33.5 I/mJ 18.8 s 1804: 14069 7.8 C/MHz 456 mW 8.1 J 30.9 I/mJ 17.8 s 1920: 14909 7.8 C/MHz 507 mW 8.5 J 29.4 I/mJ 16.8 s 2016: 15706 7.8 C/MHz 558 mW 8.9 J 28.1 I/mJ 15.9 s 2131: 16612 7.8 C/MHz 632 mW 9.5 J 26.3 I/mJ 15.1 s 2227: 17349 7.8 C/MHz 698 mW 10.1 J 24.8 I/mJ 14.4 s 2323: 18088 7.8 C/MHz 717 mW 9.9 J 25.2 I/mJ 13.8 s 2419: 18835 7.8 C/MHz 845 mW 11.2 J 22.3 I/mJ 13.3 s ===== CPU 7 ===== Frequencies: 825 940 1056 1171 1286 1401 1497 1612 1708 1804 1920 2016 2131 2227 2323 2419 2534 2649 2745 2841 825: 3215 3.9 C/MHz 158 mW 12.3 J 20.3 I/mJ 77.8 s 940: 7330 7.8 C/MHz 269 mW 9.2 J 27.3 I/mJ 34.1 s 1056: 8227 7.8 C/MHz 291 mW 8.8 J 28.2 I/mJ 30.4 s 1171: 9125 7.8 C/MHz 316 mW 8.7 J 28.9 I/mJ 27.4 s 1286: 10024 7.8 C/MHz 338 mW 8.4 J 29.6 I/mJ 25.0 s 1401: 10922 7.8 C/MHz 365 mW 8.4 J 29.9 I/mJ 22.9 s 1497: 11674 7.8 C/MHz 383 mW 8.2 J 30.4 I/mJ 21.4 s 1612: 12564 7.8 C/MHz 406 mW 8.1 J 30.9 I/mJ 19.9 s 1708: 13317 7.8 C/MHz 427 mW 8.0 J 31.2 I/mJ 18.8 s 1804: 14062 7.8 C/MHz 446 mW 7.9 J 31.5 I/mJ 17.8 s 1920: 14966 7.8 C/MHz 498 mW 8.3 J 30.1 I/mJ 16.7 s 2016: 15711 7.8 C/MHz 513 mW 8.2 J 30.6 I/mJ 15.9 s 2131: 16599 7.8 C/MHz 599 mW 9.0 J 27.7 I/mJ 15.1 s 2227: 17353 7.8 C/MHz 622 mW 9.0 J 27.9 I/mJ 14.4 s 2323: 18095 7.8 C/MHz 704 mW 9.7 J 25.7 I/mJ 13.8 s 2419: 18849 7.8 C/MHz 738 mW 9.8 J 25.5 I/mJ 13.3 s 2534: 19761 7.8 C/MHz 824 mW 10.4 J 23.9 I/mJ 12.7 s 2649: 20658 7.8 C/MHz 882 mW 10.7 J 23.4 I/mJ 12.1 s 2745: 21400 7.8 C/MHz 1003 mW 11.7 J 21.3 I/mJ 11.7 s 2841: 22147 7.8 C/MHz 1092 mW 12.3 J 20.3 I/mJ 11.3 s [1] https://github.com/kdrag0n/freqbench [2] https://www.eembc.org/coremark/ [3] https://github.com/kdrag0n/freqbench/tree/master/results/sm8150/main Signed-off-by: Danny Lin Link: https://lore.kernel.org/r/20201221002907.2870059-4-danny@kdrag0n.dev Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 1b10bc80e483..84d3c8a0b7f1 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -47,6 +47,8 @@ CPU0: cpu@0 { compatible = "qcom,kryo485"; reg = <0x0 0x0>; enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <232>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; @@ -66,6 +68,8 @@ CPU1: cpu@100 { compatible = "qcom,kryo485"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <232>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; @@ -83,6 +87,8 @@ CPU2: cpu@200 { compatible = "qcom,kryo485"; reg = <0x0 0x200>; enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <232>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; @@ -99,6 +105,8 @@ CPU3: cpu@300 { compatible = "qcom,kryo485"; reg = <0x0 0x300>; enable-method = "psci"; + capacity-dmips-mhz = <488>; + dynamic-power-coefficient = <232>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; @@ -115,6 +123,8 @@ CPU4: cpu@400 { compatible = "qcom,kryo485"; reg = <0x0 0x400>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <369>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; @@ -131,6 +141,8 @@ CPU5: cpu@500 { compatible = "qcom,kryo485"; reg = <0x0 0x500>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <369>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; @@ -147,6 +159,8 @@ CPU6: cpu@600 { compatible = "qcom,kryo485"; reg = <0x0 0x600>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <369>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; @@ -163,6 +177,8 @@ CPU7: cpu@700 { compatible = "qcom,kryo485"; reg = <0x0 0x700>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <421>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; From f772081f48831f68dc4c53f58bb28077c3cd52a7 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 6 Jan 2021 15:25:49 -0800 Subject: [PATCH 023/100] arm64: dts: qcom: sc7180: Add "dp_hot_plug_det" pinconf for trogdor We have an external pull on this line, so disable the internal pull. Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20210106152537.1.Ib4b5b0e88fdc825c0e2662bab982dda8af2297b2@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index d76200d2b373..e3a3d809448f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -936,6 +936,13 @@ wifi-firmware { /* PINCTRL - additions to nodes defined in sc7180.dtsi */ +&dp_hot_plug_det { + pinconf { + pins = "gpio117"; + bias-disable; + }; +}; + &qspi_cs0 { pinconf { pins = "gpio68"; From 826e6faf49ae1eb065759a30832a2e34740bd8b1 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 6 Jan 2021 11:21:34 +0100 Subject: [PATCH 024/100] arm64: dts: qcom: msm8916-samsung-a5u: Fix iris compatible Unlike most MSM8916 boards, samsung-a5u uses WCN3660B instead of WCN3620 to support the 5 GHz band additionally. WCN3660B has similar requirements as WCN3620, but it needs the XO clock to run at 48 MHz instead of 19.2 MHz. So far it was possible to describe that configuration using the qcom,wcn3680 compatible. However, as of commit 8490987bdb9a ("wcn36xx: Hook and identify RF_IRIS_WCN3680"), the wcn36xx driver will now use the qcom,wcn3680 compatible to enable functionality specific to WCN3680. In particular, WCN3680 supports 802.11ac, which is not available in WCN3660B. Use the new qcom,wcn3660b compatible to describe the chip properly. Fixes: 0d7051999175 ("arm64: dts: msm8916-samsung-a5u: Override iris compatible") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210106102134.59801-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index e39c04d977c2..dd35c3344358 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -38,7 +38,7 @@ touchscreen@48 { &pronto { iris { - compatible = "qcom,wcn3680"; + compatible = "qcom,wcn3660b"; }; }; From e5376f2ea2e2de4519092287382efdb226acec27 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 7 Dec 2020 14:33:02 -0800 Subject: [PATCH 025/100] arm64: dts: qcom: Clean up sc7180-trogdor voltage rails For a bunch of rails we really don't do anything with them in Linux. These are things like modem voltage rails that the modem manages these itself and core rails (like IO rails) that are setup to just automagically do the right thing by the firmware. Let's stop even listing those rails in our device tree. The net result of this is that some of these rails might be able to go down to a lower voltage or perhaps transition to LPM (low power mode) sometimes. Here's a list of what we're doing and why: * L1A - only goes to SoC and doesn't seem associated with any particular peripheral. Kernel isn't doing anything with this. Removing from dts. NET IMPACT: rail might drop from 1.2V to 1.178V and switch to LPM in some cases depending on firmware. * L2A - only goes to SoC and doesn't seem associated with any particular peripheral. Kernel isn't doing anything with this. Removing from dts. NET IMPACT: rail might switch to LPM in some cases depending on firmware. * L3A - only goes to SoC and doesn't seem associated with any particular peripheral. Kernel isn't doing anything with this. Removing from dts. NET IMPACT: rail might switch to LPM in some cases depending on firmware. * L5A - seems to be totally unused as far as I can tell and doesn't even come off QSIP. Removing from dts. * L6A - only goes to SoC and doesn't seem associated with any particular peripheral (I think?). Kernel isn't doing anything with this. Removing from dts. NET IMPACT: rail might switch to LPM in some cases depending on firmware. * L16A - Looks like this is only used for internal RF stuff. Removing from dts. NET IMPACT: rail might switch to LPM in some cases depending on firmware. * L1C - Just goes to WiFi / Bluetooth. Trust how IDP has this set and put this back at 1.616V min. * L4C - This goes out to the eSIM among other places. This looks like it's intended to be for SIM card and modem manages. NET IMPACT: rail might switch to LPM in some cases depending on firmware. * L5C - This goes to the physical SIM. This looks like it's intended to be for SIM card and modem manages. NET IMPACT: rail might drop from 1.8V to 1.648V and switch to LPM in some cases depending on firmware. NOTE: in general for anything which is supposed to be managed by Linux I still left it all forced to HPM since I'm not 100% sure that all the needed calls to regulator_set_load() are in place and HPM is safer. Switching more things to LPM can happen in a future patch. ALSO NOTE: Power measurements showed no measurable difference after applying this patch, so perhaps it should be viewed more as a cleanup than any power savings. Reviewed-by: Alexandru M Stan Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20201207143255.1.Ib92ec35163682dec4b2fbb4bde0785cb6e6dde27@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 82 ++------------------ 1 file changed, 7 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index e3a3d809448f..07c8b2c926c0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -298,40 +298,6 @@ pp1125_s1a: smps1 { regulator-max-microvolt = <1128000>; }; - /* - * pp2040_s5a (smps5) and pp1056_s4a (smps4) are just - * inputs to other rails on AOP-managed PMICs on trogdor. - * The system is already configured to manage these rails - * automatically (enable when needed, adjust voltage for - * headroom) so we won't specify anything here. - * - * NOTE: though the rails have a voltage implied by their - * name, the automatic headroom calculation might not result - * in them being that voltage. ...and that's OK. - * Specifically the only point of these rails is to provide - * an input source for other rails and if we can satisify the - * needs of those other rails with a lower source voltage then - * we save power. - */ - - pp1200_l1a: ldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - pp1000_l2a: ldo2 { - regulator-min-microvolt = <944000>; - regulator-max-microvolt = <1056000>; - regulator-initial-mode = ; - }; - - pp1000_l3a: ldo3 { - regulator-min-microvolt = <968000>; - regulator-max-microvolt = <1064000>; - regulator-initial-mode = ; - }; - vdd_qlink_lv: vdd_qlink_lv_ck: vdd_qusb_hs0_core: @@ -350,24 +316,6 @@ pp900_l4a: ldo4 { regulator-initial-mode = ; }; - pp2700_l5a: ldo5 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - ebi0_cal: - ebi1_cal: - vddio_ck_ebi0: - vddio_ck_ebi1: - vddio_ebi0: - vddq: - pp600_l6a: ldo6 { - regulator-min-microvolt = <568000>; - regulator-max-microvolt = <648000>; - regulator-initial-mode = ; - }; - vdd_cx_wlan: pp800_l9a: ldo9 { regulator-min-microvolt = <488000>; @@ -404,6 +352,11 @@ pp1800_l12a_r: ldo12 { regulator-initial-mode = ; }; + /* + * On trogdor this needs to match l10a since we use it to + * give power to things like SPI flash which communicate back + * on lines powered by l10a. Thus we force to 1.8V. + */ pp1800_l13a: ldo13 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -424,12 +377,6 @@ pp1800_l15a: ldo15 { regulator-initial-mode = ; }; - pp2700_l16a: ldo16 { - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - vdda_qusb_hs0_3p1: vdd_pdphy: pp3100_l17a: ldo17 { @@ -463,8 +410,8 @@ pp1300_s8c: smps8 { }; pp1800_l1c: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; regulator-initial-mode = ; }; @@ -491,21 +438,6 @@ pp1200_l3c: ldo3 { regulator-initial-mode = ; }; - ld_pp1800_esim_l4c: - vddpx_5: - pp1800_l4c: ldo4 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - vddpx_6: - pp1800_l5c: ldo5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - vddpx_2: ppvar_l6c: ldo6 { regulator-min-microvolt = <1800000>; From b2e3f897684ccc03139c8455e17abcc27bb5d491 Mon Sep 17 00:00:00 2001 From: Danny Lin Date: Tue, 5 Jan 2021 12:10:00 -0800 Subject: [PATCH 026/100] arm64: dts: qcom: sm8150: Add support for deep CPU cluster idle This commit adds support for deep idling of the entire unified DynamIQ CPU cluster on sm8150. In this idle state, the LLCC (Last-Level Cache Controller) is powered off and the AOP (Always-On Processor) enters a low-power sleep state. I'm not sure what the per-CPU 0x400000f4 idle state previously contributed by Qualcomm as the "cluster sleep" state is, but the downstream kernel has no such state. The real deep cluster idle state is 0x41000c244, composed of: Cluster idle state: (0xc24) << 4 = 0xc240 Is reset state: 1 << 30 = 0x40000000 Affinity level: 1 << 24 = 0x1000000 CPU idle state: 0x4 (power collapse) This setup can be replicated with the PSCI power domain cpuidle driver, which utilizes OSI to enter cluster idle when the last active CPU enters idle. The cluster idle state cannot be used as a plain cpuidle state because it requires that all CPUs in the cluster are idling. Reviewed-by: Ulf Hansson Signed-off-by: Danny Lin Link: https://lore.kernel.org/r/20210105201000.913183-1-danny@kdrag0n.dev Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++------ 1 file changed, 73 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 84d3c8a0b7f1..9a939c6095ea 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -49,10 +49,10 @@ CPU0: cpu@0 { enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -70,10 +70,10 @@ CPU1: cpu@100 { enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -89,10 +89,10 @@ CPU2: cpu@200 { enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -107,10 +107,10 @@ CPU3: cpu@300 { enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -125,10 +125,10 @@ CPU4: cpu@400 { enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -143,10 +143,10 @@ CPU5: cpu@500 { enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -161,10 +161,10 @@ CPU6: cpu@600 { enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -179,10 +179,10 @@ CPU7: cpu@700 { enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <421>; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -248,11 +248,13 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 { min-residency-us = <4488>; local-timer-stop; }; + }; + domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; + compatible = "domain-idle-state"; idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x400000F4>; + arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; @@ -288,6 +290,59 @@ pmu { psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; }; reserved-memory { From 8f03014019f4afab7209f31edd584fcaed62c455 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 15 Jan 2021 05:41:56 +0300 Subject: [PATCH 027/100] arm64: dts: qcom: qrb5165-rb5: enable cdsp device Enable Compute DSP (cdsp) on QRB5165-RB5 platform and provide firmware filename used to boot the cdsp. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210115024156.92265-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 477ff91dc460..2d713e0c7d6a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -444,6 +444,11 @@ vreg_s8c_1p3: smps8 { }; }; +&cdsp { + status = "okay"; + firmware-name = "qcom/sm8250/cdsp.mbn"; +}; + &dsi0 { status = "okay"; vdda-supply = <&vreg_l9a_1p2>; From c2c76ddb140291724482028327bd648944571ff5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 15 Jan 2021 05:47:13 +0300 Subject: [PATCH 028/100] arm64: dts: qcom: qrb5165-rb5: add HDMI audio playback Add support for audio output over the HDMI output using Tertiary I2S and LT9611UXC DSI-to-HDMI bridge. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210115024713.92574-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 2d713e0c7d6a..7c2a798c6ac6 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -697,6 +697,7 @@ &sound { "VA DMIC0", "vdd-micb", "VA DMIC1", "vdd-micb", "MM_DL1", "MultiMedia1 Playback", + "MM_DL2", "MultiMedia2 Playback", "MultiMedia3 Capture", "MM_UL3"; mm1-dai-link { @@ -706,6 +707,13 @@ cpu { }; }; + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + mm3-dai-link { link-name = "MultiMedia3"; cpu { @@ -713,6 +721,21 @@ cpu { }; }; + hdmi-dai-link { + link-name = "HDMI Playback"; + cpu { + sound-dai = <&q6afedai TERTIARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <<9611_codec 0>; + }; + }; + dma-dai-link { link-name = "WSA Playback"; cpu { From 74097d805edb9305a2a588a8ece82d2495ff5a88 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 9 Jan 2021 04:12:52 +0300 Subject: [PATCH 029/100] arm64: dts: qcom: sm8250: correct sdhc_2 xo clk sdhc_2 uses 19200000 Hz clock rather than wrongly specified xo_board (39400000 Hz). Specify correct clock to fix DLL setup for SDR104 mode. Signed-off-by: Dmitry Baryshkov Fixes: c4cf0300be84 ("arm64: dts: qcom: sm8250: Add support for SDC2") Link: https://lore.kernel.org/r/20210109011252.3436533-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 6b4cf4426859..1c3ab5a3783d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1825,7 +1825,7 @@ sdhc_2: sdhci@8804000 { clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x4a0 0x0>; qcom,dll-config = <0x0007642c>; From 288ef8a42612df516e2e598a9ca5b3d9be846290 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 14 Jan 2021 20:31:57 +0000 Subject: [PATCH 030/100] arm64: dts: sdm845: add oneplus6/6t devices Add initial support for the OnePlus 6 (enchilada) and 6T (fajita) based on the sdm845-mtp DT with the following functionality: * Touch * Display * GPU * Wlan and Bluetooth * USB peripheral mode * Remoteproc Reviewed-by: Konrad Dybcio Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20210114203057.64541-2-caleb@connolly.tech Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 623 ++++++++++++++++++ .../dts/qcom/sdm845-oneplus-enchilada.dts | 19 + .../boot/dts/qcom/sdm845-oneplus-fajita.dts | 23 + 4 files changed, 667 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6a4be237f344..b5d86739f781 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -44,6 +44,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi new file mode 100644 index 000000000000..8f617f7b6d34 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 OnePlus 6(T) (enchilada / fajita) common device tree source + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &rmtfs_mem; + +/ { + aliases { + hsuart0 = &uart6; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "Volume keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_down_gpio &volume_up_gpio>; + + vol-down { + label = "Volume down"; + linux,code = ; + gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + + vol-up { + label = "Volume up"; + linux,code = ; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + reserved-memory { + /* + * The rmtfs memory region in downstream is 'dynamically allocated' + * but given the same address every time. Hard code it as this address is + * where the modem firmware expects it to be. + */ + rmtfs_mem: memory@f5b01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf5b01000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + /* + * It seems like reserving the old rmtfs_mem region is also needed to prevent + * random crashes which are most likely modem related, more testing needed. + */ + removed_region: memory@88f00000 { + no-map; + reg = <0 0x88f00000 0 0x200000>; + }; + + ramoops: ramoops@ac300000 { + compatible = "ramoops"; + reg = <0 0xac300000 0 0x400000>; + record-size = <0x40000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size = <0x200000>; + devinfo-size = <0x1000>; + ecc-size = <16>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* + * Apparently RPMh does not provide support for PM8998 S4 because it + * is always-on; model it as a fixed regulator. + */ + vreg_s4a_1p8: pm8998-smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + /* + * The touchscreen regulator seems to be controlled somehow by a gpio. + * Model it as a fixed regulator and keep it on. Without schematics we + * don't know how this is actually wired up... + */ + ts_1p8_supply: ts-1p8-regulator { + compatible = "regulator-fixed"; + regulator-name = "ts_1p8_supply"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 88 0>; + enable-active-high; + regulator-boot-on; + }; +}; + +&adsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/oneplus6/adsp.mbn"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdda_mipi_dsi0_pll: + vdda_qlink_lv: + vdda_ufs1_core: + vdda_usb1_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdda_qusb_hs0_1p8: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_mipi_dsi0_1p2: + vdda_ufs1_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&cdsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn"; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + #address-cells = <1>; + #size-cells = <0>; + + /* + * Both devices use different panels but all other properties + * are common. Compatible line is declared in device dts. + */ + display_panel: panel@0 { + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_pins &panel_te_pin &panel_esd_pin>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&gpu { + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; + }; +}; + +&i2c12 { + status = "okay"; + clock-frequency = <400000>; + + synaptics-rmi4-i2c@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_default_pins>; + + vdd-supply = <&vreg_l28a_3p0>; + vio-supply = <&ts_1p8_supply>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <200>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4_f12: rmi4-f12@12 { + reg = <0x12>; + touchscreen-x-mm = <68>; + touchscreen-y-mm = <144>; + syna,sensor-type = <1>; + syna,rezero-wait-ms = <200>; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +/* Modem/wifi*/ +&mss_pil { + status = "okay"; + firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn"; +}; + +&pm8998_gpio { + volume_down_gpio: pm8998_gpio5 { + pinconf { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <0>; + }; + }; + + volume_up_gpio: pm8998_gpio6 { + pinconf { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <0>; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qup_i2c12_default { + mux { + pins = "gpio49", "gpio50"; + function = "qup12"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_i2c10_default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_uart9_default { + pinconf-tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +/* + * Prevent garbage data on bluetooth UART lines + */ +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + cts { + pins = "gpio45"; + bias-pull-down; + }; + + rts-tx { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio48"; + bias-pull-up; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + /* + * This path is relative to the qca/ + * subdir under lib/firmware. + */ + firmware-name = "oneplus6/crnv21.bin"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + +&usb_1 { + status = "okay"; + + /* + * disable USB3 clock requirement as the device only supports + * USB2. + */ + qcom,select-utmi-as-pipe-clk; +}; + +&usb_1_dwc3 { + /* + * We don't have the capability to switch modes yet. + */ + dr_mode = "peripheral"; + + /* fastest mode for USB 2 */ + maximum-speed = "high-speed"; + + /* Remove USB3 phy as it's unused on this device. */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + tri_state_key_default: tri_state_key_default { + mux { + pins = "gpio40", "gpio42", "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + ts_default_pins: ts-int { + mux { + pins = "gpio99", "gpio125"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + panel_reset_pins: panel-reset { + mux { + pins = "gpio6", "gpio25", "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + panel_te_pin: panel-te { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + panel_esd_pin: panel-esd { + mux { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; +}; + +&wifi { + status = "okay"; + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts new file mode 100644 index 000000000000..72842c887617 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 OnePlus 6 (enchilada) device tree. + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include "sdm845-oneplus-common.dtsi" + +/ { + model = "OnePlus 6"; + compatible = "oneplus,enchilada", "qcom,sdm845"; +}; + +&display_panel { + status = "okay"; + + compatible = "samsung,sofef00"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts new file mode 100644 index 000000000000..969b36dc9e2c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 OnePlus 6T (fajita) device tree. + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include "sdm845-oneplus-common.dtsi" + +/ { + model = "OnePlus 6T"; + compatible = "oneplus,fajita", "qcom,sdm845"; +}; + +&display_panel { + status = "okay"; + + compatible = "samsung,s6e3fc2x01"; +}; + +&rmi4_f12 { + touchscreen-y-mm = <148>; +}; From 6be4ba5467bed412f1e68a8aa1e22279bfb8fcd5 Mon Sep 17 00:00:00 2001 From: Steev Klimaszewski Date: Tue, 12 Jan 2021 17:06:40 +0800 Subject: [PATCH 031/100] arm64: dts: sdm850: Add OPP tables for 2.84 and 2.96GHz Running cpufreq-hw driver on Lenovo Yoga C630 laptop, the following warning messages will be seen. [ 3.415340] cpu cpu4: Voltage update failed freq=2841600 [ 3.418755] cpu cpu4: failed to update OPP for freq=2841600 [ 3.422949] cpu cpu4: Voltage update failed freq=2956800 [ 3.427086] cpu cpu4: failed to update OPP for freq=2956800 This is because the cpufreq-hw lookup table of SDM850 provides these two set-points, but they are missing from OPP table in DT. Let's create sdm850.dtsi to add the OPP for them, so that the warning will be gone. Signed-off-by: Steev Klimaszewski Signed-off-by: Shawn Guo Link: https://lore.kernel.org/r/20210112090640.20062-1-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 2 +- arch/arm64/boot/dts/qcom/sdm850.dtsi | 21 +++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/sdm850.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 13fdd02cffe6..94705d02f46c 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -13,7 +13,7 @@ #include #include #include -#include "sdm845.dtsi" +#include "sdm850.dtsi" #include "pm8998.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sdm850.dtsi b/arch/arm64/boot/dts/qcom/sdm850.dtsi new file mode 100644 index 000000000000..b1c2cf566c7a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm850.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM850 SoC device tree source + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include "sdm845.dtsi" + +&cpu4_opp_table { + cpu4_opp33: opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <7216000 25497600>; + }; + + cpu4_opp34: opp-2956800000 { + opp-hz = /bits/ 64 <2956800000>; + opp-peak-kBps = <7216000 25497600>; + turbo-mode; + }; +}; From 3716a583fe0bbe3babf4ce260064a7fa13d6d989 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 11 Jan 2021 18:53:58 +0100 Subject: [PATCH 032/100] arm64: dts: qcom: msm8916-samsung-a2015: Fix sensors When the BMC150 accelerometer/magnetometer was added to the device tree, the sensors were working without specifying any regulator supplies, likely because the regulators were on by default and then never turned off. For some reason, this is no longer the case for pm8916_l17, which prevents the sensors from working in some cases. Now that the bmc150_accel/bmc150_magn drivers can enable necessary regulators, declare the necessary regulator supplies to make the sensors work again. Fixes: 079f81acf10f ("arm64: dts: qcom: msm8916-samsung-a2015: Add accelerometer/magnetometer") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210111175358.97171-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index f91269492d72..f1af798abd74 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -106,6 +106,9 @@ accelerometer: accelerometer@10 { interrupt-parent = <&msmgpio>; interrupts = <115 IRQ_TYPE_EDGE_RISING>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + pinctrl-names = "default"; pinctrl-0 = <&accel_int_default>; }; @@ -113,6 +116,9 @@ accelerometer: accelerometer@10 { magnetometer@12 { compatible = "bosch,bmc150_magn"; reg = <0x12>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; }; }; From b4791e695526939be3c4f043fe69222d2ba7c171 Mon Sep 17 00:00:00 2001 From: Danny Lin Date: Mon, 11 Jan 2021 17:32:53 -0800 Subject: [PATCH 033/100] arm64: dts: qcom: sm8250: Define CPU topology sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within the same CPU cluster and LLC (Last-Level Cache) domain. Define this topology to help the scheduler make decisions. Signed-off-by: Danny Lin Link: https://lore.kernel.org/r/20210112013255.415253-1-danny@kdrag0n.dev Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 1c3ab5a3783d..8d5c5d44187a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -203,6 +203,42 @@ L2_700: l2-cache { next-level-cache = <&L3_0>; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; }; firmware { From 6aabed5526ee2cbe377b9b19cbb2cbb832bdfb22 Mon Sep 17 00:00:00 2001 From: Danny Lin Date: Mon, 11 Jan 2021 17:32:54 -0800 Subject: [PATCH 034/100] arm64: dts: qcom: sm8250: Add CPU capacities and energy model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Power and performance measurements were made using my freqbench [1] benchmark coordinator, which isolates, offlines, and disables the timer tick on test CPUs to maximize accuracy. It uses EEMBC CoreMark [2] as the workload and measures power usage using the PM8150B PMIC's fuel gauge. The energy model dynamic-power-coefficient values were calculated with DPC = µW / MHz / V^2 for each OPP, and averaged across all OPPs within each cluster for the final coefficient. Voltages were obtained from the qcom-cpufreq-hw driver that reads voltages from the OSM LUT programmed into the SoC. Normalized DMIPS/MHz capacity scale values for each CPU were calculated from CoreMarks/MHz (CoreMark iterations per second per MHz), which serves the same purpose. For each CPU, the final capacity-dmips-mhz value is the C/MHz value of its maximum frequency normalized to SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system. A Xiaomi Redmi K30S Ultra device running a downstream Qualcomm 4.19 kernel was used for benchmarking to ensure proper frequency scaling and other low-level controls. Raw benchmark results can be found in the freqbench repository [3]. Below is a human-readable summary: Frequency domains: cpu1 cpu4 cpu7 Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 Baseline power usage: 1223 mW ===== CPU 1 ===== Frequencies: 300 403 518 614 691 787 883 979 1075 1171 1248 1344 1420 1516 1612 1708 1804 300: 1114 3.7 C/MHz 29 mW 6.4 J 39.0 I/mJ 224.5 s 403: 1497 3.7 C/MHz 33 mW 5.5 J 45.2 I/mJ 167.0 s 518: 1925 3.7 C/MHz 48 mW 6.3 J 39.7 I/mJ 129.9 s 614: 2281 3.7 C/MHz 73 mW 8.0 J 31.1 I/mJ 109.6 s 691: 2566 3.7 C/MHz 46 mW 4.5 J 55.2 I/mJ 97.4 s 787: 2923 3.7 C/MHz 86 mW 7.4 J 33.8 I/mJ 85.5 s 883: 3279 3.7 C/MHz 77 mW 5.9 J 42.5 I/mJ 76.2 s 979: 3635 3.7 C/MHz 65 mW 4.4 J 56.2 I/mJ 68.8 s 1075: 3992 3.7 C/MHz 71 mW 4.4 J 56.2 I/mJ 62.6 s 1171: 4348 3.7 C/MHz 121 mW 6.9 J 36.0 I/mJ 57.5 s 1248: 4633 3.7 C/MHz 79 mW 4.2 J 58.9 I/mJ 54.0 s 1344: 4990 3.7 C/MHz 81 mW 4.0 J 61.7 I/mJ 50.1 s 1420: 5275 3.7 C/MHz 85 mW 4.0 J 61.8 I/mJ 47.4 s 1516: 5632 3.7 C/MHz 88 mW 3.9 J 64.3 I/mJ 44.4 s 1612: 5988 3.7 C/MHz 92 mW 3.8 J 65.4 I/mJ 41.7 s 1708: 6346 3.7 C/MHz 96 mW 3.8 J 66.3 I/mJ 39.4 s 1804: 6701 3.7 C/MHz 105 mW 3.9 J 63.5 I/mJ 37.3 s ===== CPU 4 ===== Frequencies: 710 825 940 1056 1171 1286 1382 1478 1574 1670 1766 1862 1958 2054 2150 2246 2342 2419 710: 6022 8.5 C/MHz 123 mW 5.1 J 49.1 I/mJ 41.5 s 825: 7001 8.5 C/MHz 142 mW 5.1 J 49.4 I/mJ 35.7 s 940: 7987 8.5 C/MHz 164 mW 5.1 J 48.7 I/mJ 31.3 s 1056: 8954 8.5 C/MHz 185 mW 5.2 J 48.3 I/mJ 27.9 s 1171: 9944 8.5 C/MHz 212 mW 5.3 J 46.9 I/mJ 25.2 s 1286: 10926 8.5 C/MHz 235 mW 5.4 J 46.4 I/mJ 22.9 s 1382: 11735 8.5 C/MHz 253 mW 5.4 J 46.4 I/mJ 21.3 s 1478: 12531 8.5 C/MHz 277 mW 5.5 J 45.2 I/mJ 20.0 s 1574: 13335 8.5 C/MHz 306 mW 5.7 J 43.6 I/mJ 18.8 s 1670: 14169 8.5 C/MHz 335 mW 5.9 J 42.2 I/mJ 17.7 s 1766: 14969 8.5 C/MHz 353 mW 5.9 J 42.3 I/mJ 16.7 s 1862: 15800 8.5 C/MHz 444 mW 7.0 J 35.6 I/mJ 15.8 s 1958: 16630 8.5 C/MHz 463 mW 7.0 J 35.9 I/mJ 15.0 s 2054: 17428 8.5 C/MHz 480 mW 6.9 J 36.3 I/mJ 14.4 s 2150: 18238 8.5 C/MHz 496 mW 6.8 J 36.8 I/mJ 13.7 s 2246: 19053 8.5 C/MHz 578 mW 7.6 J 32.9 I/mJ 13.1 s 2342: 19873 8.5 C/MHz 625 mW 7.9 J 31.8 I/mJ 12.6 s 2419: 20522 8.5 C/MHz 675 mW 8.2 J 30.4 I/mJ 12.2 s ===== CPU 7 ===== Frequencies: 844 960 1075 1190 1305 1401 1516 1632 1747 1862 1977 2073 2169 2265 2361 2457 2553 2649 2745 2841 844: 7172 8.5 C/MHz 155 mW 5.4 J 46.4 I/mJ 34.9 s 960: 8148 8.5 C/MHz 172 mW 5.3 J 47.4 I/mJ 30.7 s 1075: 9116 8.5 C/MHz 197 mW 5.4 J 46.2 I/mJ 27.4 s 1190: 10105 8.5 C/MHz 220 mW 5.4 J 46.0 I/mJ 24.8 s 1305: 11084 8.5 C/MHz 242 mW 5.5 J 45.8 I/mJ 22.6 s 1401: 11888 8.5 C/MHz 262 mW 5.5 J 45.4 I/mJ 21.0 s 1516: 12859 8.5 C/MHz 297 mW 5.8 J 43.2 I/mJ 19.5 s 1632: 13840 8.5 C/MHz 335 mW 6.1 J 41.3 I/mJ 18.1 s 1747: 14827 8.5 C/MHz 369 mW 6.2 J 40.1 I/mJ 16.9 s 1862: 15800 8.5 C/MHz 395 mW 6.3 J 40.0 I/mJ 15.8 s 1977: 16786 8.5 C/MHz 443 mW 6.6 J 37.9 I/mJ 14.9 s 2073: 17566 8.5 C/MHz 488 mW 6.9 J 36.0 I/mJ 14.2 s 2169: 18395 8.5 C/MHz 620 mW 8.4 J 29.7 I/mJ 13.6 s 2265: 19223 8.5 C/MHz 621 mW 8.1 J 30.9 I/mJ 13.0 s 2361: 20040 8.5 C/MHz 672 mW 8.4 J 29.8 I/mJ 12.5 s 2457: 20852 8.5 C/MHz 696 mW 8.3 J 29.9 I/mJ 12.0 s 2553: 21684 8.5 C/MHz 738 mW 8.5 J 29.3 I/mJ 11.5 s 2649: 22458 8.5 C/MHz 793 mW 8.8 J 28.3 I/mJ 11.1 s 2745: 23314 8.5 C/MHz 875 mW 9.4 J 26.6 I/mJ 10.7 s 2841: 24103 8.5 C/MHz 928 mW 9.6 J 26.0 I/mJ 10.4 s [1] https://github.com/kdrag0n/freqbench [2] https://www.eembc.org/coremark/ [3] https://github.com/kdrag0n/freqbench/tree/master/results/sm8250/k30s Signed-off-by: Danny Lin Link: https://lore.kernel.org/r/20210112013255.415253-2-danny@kdrag0n.dev Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 8d5c5d44187a..20e70d5641ea 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -93,6 +93,8 @@ CPU0: cpu@0 { compatible = "qcom,kryo485"; reg = <0x0 0x0>; enable-method = "psci"; + capacity-dmips-mhz = <448>; + dynamic-power-coefficient = <205>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -110,6 +112,8 @@ CPU1: cpu@100 { compatible = "qcom,kryo485"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <448>; + dynamic-power-coefficient = <205>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -124,6 +128,8 @@ CPU2: cpu@200 { compatible = "qcom,kryo485"; reg = <0x0 0x200>; enable-method = "psci"; + capacity-dmips-mhz = <448>; + dynamic-power-coefficient = <205>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -138,6 +144,8 @@ CPU3: cpu@300 { compatible = "qcom,kryo485"; reg = <0x0 0x300>; enable-method = "psci"; + capacity-dmips-mhz = <448>; + dynamic-power-coefficient = <205>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; @@ -152,6 +160,8 @@ CPU4: cpu@400 { compatible = "qcom,kryo485"; reg = <0x0 0x400>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <379>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; @@ -166,6 +176,8 @@ CPU5: cpu@500 { compatible = "qcom,kryo485"; reg = <0x0 0x500>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <379>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; @@ -181,6 +193,8 @@ CPU6: cpu@600 { compatible = "qcom,kryo485"; reg = <0x0 0x600>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <379>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; @@ -195,6 +209,8 @@ CPU7: cpu@700 { compatible = "qcom,kryo485"; reg = <0x0 0x700>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <444>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; From bc19af98ba391aa04c2e3b070a1a28eac43c9143 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Fri, 8 Jan 2021 14:16:50 -0800 Subject: [PATCH 035/100] arm64: dts: qcom: sc7180: Add labels for cpuN-thermal nodes Add labels to the cpuN-thermal nodes to allow board files to use a phandle instead replicating the node hierarchy when adjusting certain properties. Due to the 'sustainable-power' property CPU thermal zones are more likely to need property updates than other SC7180 zones, hence only labels for CPU zones are added for now. Reviewed-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20210108141648.1.Ia8019b8b303ca31a06752ed6ceb5c3ac50bd1d48@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 268fa40a1774..2bd06beafecc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3590,7 +3590,7 @@ lpass_hm: clock-controller@63000000 { }; thermal-zones { - cpu0-thermal { + cpu0_thermal: cpu0-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -3639,7 +3639,7 @@ map1 { }; }; - cpu1-thermal { + cpu1_thermal: cpu1-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -3688,7 +3688,7 @@ map1 { }; }; - cpu2-thermal { + cpu2_thermal: cpu2-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -3737,7 +3737,7 @@ map1 { }; }; - cpu3-thermal { + cpu3_thermal: cpu3-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -3786,7 +3786,7 @@ map1 { }; }; - cpu4-thermal { + cpu4_thermal: cpu4-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -3835,7 +3835,7 @@ map1 { }; }; - cpu5-thermal { + cpu5_thermal: cpu5-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -3884,7 +3884,7 @@ map1 { }; }; - cpu6-thermal { + cpu6_thermal: cpu6-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -3925,7 +3925,7 @@ map1 { }; }; - cpu7-thermal { + cpu7_thermal: cpu7-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -3966,7 +3966,7 @@ map1 { }; }; - cpu8-thermal { + cpu8_thermal: cpu8-thermal { polling-delay-passive = <250>; polling-delay = <0>; @@ -4007,7 +4007,7 @@ map1 { }; }; - cpu9-thermal { + cpu9_thermal: cpu9-thermal { polling-delay-passive = <250>; polling-delay = <0>; From abf2c58aaa776cf43daf0fc4fd20082c71583c6b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 17 Dec 2020 21:33:41 +0300 Subject: [PATCH 036/100] arm64: dts: qcom: qrb5165-rb5: fix uSD pins drive strength Lower drive strength for microSD data and CMD pins from 16 to 10. This fixes spurious card removal issues observed on some boards. Also this change allows us to re-enable 1.8V support, which seems to work with lowered drive strength. Signed-off-by: Dmitry Baryshkov Cc: Veerabhadrarao Badiganti Fixes: 53a8ccf1c7e5 ("arm64: dts: qcom: rb5: Add support for uSD card") Link: https://lore.kernel.org/r/20201217183341.3186402-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 7c2a798c6ac6..4a0c3edf87e1 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -660,8 +660,6 @@ &sdhc_2 { vqmmc-supply = <&vreg_l6c_2p96>; cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; bus-width = <4>; - /* there seem to be issues with HS400-1.8V mode, so disable it */ - no-1-8-v; no-sdio; no-emmc; }; @@ -982,13 +980,13 @@ clk { cmd { pins = "sdc2_cmd"; bias-pull-up; - drive-strength = <16>; + drive-strength = <10>; }; data { pins = "sdc2_data"; bias-pull-up; - drive-strength = <16>; + drive-strength = <10>; }; }; From 0fb56bf95c76f99d6301aea8f7198babd0005fa6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 16 Jan 2021 03:23:46 +0300 Subject: [PATCH 037/100] arm64: dts: qcom: qrb5165-rb5: sort nodes alphabetically Move swr0 device node to keep alphabetical sorting order of device tree nodes. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210116002346.422479-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 40 ++++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 4a0c3edf87e1..a424595da8b0 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -664,26 +664,6 @@ &sdhc_2 { no-emmc; }; -&swr0 { - left_spkr: wsa8810-left{ - compatible = "sdw10217211000"; - reg = <0 3>; - powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrLeft"; - #sound-dai-cells = <0>; - }; - - right_spkr: wsa8810-right{ - compatible = "sdw10217211000"; - reg = <0 4>; - powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; - #thermal-sensor-cells = <0>; - sound-name-prefix = "SpkrRight"; - #sound-dai-cells = <0>; - }; -}; - &sound { compatible = "qcom,qrb5165-rb5-sndcard"; pinctrl-0 = <&tert_mi2s_active>; @@ -780,6 +760,26 @@ can@0 { }; }; +&swr0 { + left_spkr: wsa8810-left{ + compatible = "sdw10217211000"; + reg = <0 3>; + powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: wsa8810-right{ + compatible = "sdw10217211000"; + reg = <0 4>; + powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; +}; + &tlmm { gpio-reserved-ranges = <40 4>; gpio-line-names = From d4863ef399a29cae3001b3fedfd2864e651055ba Mon Sep 17 00:00:00 2001 From: Robert Foss Date: Mon, 21 Dec 2020 11:09:55 +0100 Subject: [PATCH 038/100] arm64: dts: qcom: sdm845-db845c: Fix reset-pin of ov8856 node Switch reset pin of ov8856 node from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW, this issue prevented the ov8856 from probing properly as it did not respon to I2C messages. Fixes: d4919a44564b ("arm64: dts: qcom: sdm845-db845c: Add ov8856 & ov7251 camera nodes") Signed-off-by: Robert Foss Link: https://lore.kernel.org/r/20201221100955.148584-1-robert.foss@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 7cc236575ee2..f749672c5fdc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1112,11 +1112,11 @@ camera@10 { reg = <0x10>; // CAM0_RST_N - reset-gpios = <&tlmm 9 0>; + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&cam0_default>; gpios = <&tlmm 13 0>, - <&tlmm 9 0>; + <&tlmm 9 GPIO_ACTIVE_LOW>; clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; clock-names = "xvclk"; From 6243905da788cc75d920864fd087b334bb68bb7c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 19 Jan 2021 18:44:21 +0100 Subject: [PATCH 039/100] arm64: dts: pmi8998: Add the right interrupts for LAB/IBB SCP and OCP In commit 208921bae696 ("arm64: dts: qcom: pmi8998: Add nodes for LAB and IBB regulators") bindings for the lab/ibb regulators were added to the pmi8998 dt, but the original committer has never specified what the interrupts were for. LAB and IBB regulators provide two interrupts, SC-ERR (short circuit error) and VREG-OK but, in that commit, the regulators were provided with two different types of interrupts; specifically, IBB had the SC-ERR interrupt, while LAB had the VREG-OK one, none of which were (luckily) used, since the driver didn't actually use these at all. Assuming that the original intention was to have the SC IRQ in both LAB and IBB, as per the names appearing in documentation, fix the SCP interrupt. While at it, also add the OCP interrupt in order to be able to enable the Over-Current Protection feature, if requested. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210119174421.226541-8-angelogioacchino.delregno@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index d016b12967eb..d230c510d4b7 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -30,11 +30,15 @@ labibb { compatible = "qcom,pmi8998-lab-ibb"; ibb: ibb { - interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>; + interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>, + <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sc-err", "ocp"; }; lab: lab { - interrupts = <0x3 0xde 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sc-err", "ocp"; }; }; }; From 28a7eb65d474740f015e3d99bff685283b8c9289 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 19 Jan 2021 08:48:46 +0300 Subject: [PATCH 040/100] arm64: dts: qcom: pm8150x: add definitions for adc-tm5 part Define adc-tm5 thermal monitoring part. Individual channes and thermal zones are to be configured in per-device dts files. Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210119054848.592329-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pm8150b.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pm8150l.dtsi | 10 ++++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index a53eccf2b695..15e87153a194 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -97,6 +97,16 @@ die-temp@6 { }; }; + pm8150_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm8150_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index e112e8876db6..8e2f3250c914 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -95,6 +95,16 @@ chg-temp@9 { }; }; + pm8150b_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm8150b_gpios: gpio@c000 { compatible = "qcom,pm8150b-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 62139538b7d9..9f214ceec2b7 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -89,6 +89,16 @@ die-temp@6 { }; }; + pm8150l_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm8150l_gpios: gpio@c000 { compatible = "qcom,pm8150l-gpio"; reg = <0xc000>; From 681db16a5bcf3ab100318a9979b8838079fcee4d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 19 Jan 2021 08:48:47 +0300 Subject: [PATCH 041/100] arm64: dts: sm8250-mtp: add thermal zones using pmic's adc-tm5 Port thermal zones definitions from msm-4.19 tree. Enable and add channel configuration to PMIC's ADC-TM definitions. Declare thermal zones and respective trip points. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210119054848.592329-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 209 ++++++++++++++++++++++++ 1 file changed, 209 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 767a2e446248..5b4c5b08434c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -24,6 +24,106 @@ chosen { stdout-path = "serial0:115200n8"; }; + thermal-zones { + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -392,6 +492,115 @@ &i2c15 { /* rtc6226 @ 64 */ }; +&pm8150_adc { + xo-therm@4c { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm1@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + skin-therm@1 { + reg = <1>; + io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm1@2 { + reg = <2>; + io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8150b_adc { + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_adc_tm { + status = "okay"; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8150l_adc_tm { + status = "okay"; + + camera-flash-therm@0 { + reg = <0>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + skin-msm-therm@1 { + reg = <1>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm2@2 { + reg = <2>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8150l_adc { + camera-flash-therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin-msm-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa-therm2@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + &pm8150_rtc { status = "okay"; }; From 687cc021d70022136a4fe5c34a56ea897543c061 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 19 Jan 2021 08:48:48 +0300 Subject: [PATCH 042/100] arm64: dts: qrb5165-rb5: port thermal zone definitions Add thermal zones definitions basing on the downstream kernel. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210119054848.592329-6-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 155 +++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index a424595da8b0..58b94ce362b2 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -99,6 +99,78 @@ lt9611_3v3: lt9611-3v3 { regulator-always-on; }; + thermal-zones { + conn-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + pm8150l-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 1>; + + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + skin-msm-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150l_adc_tm 0>; + + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + wifi-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 1>; + + trips { + active-config0 { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8150_adc_tm 0>; + + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + }; + vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; @@ -551,6 +623,38 @@ &mdss_mdp { status = "okay"; }; +&pm8150_adc { + xo-therm@4c { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + wifi-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + wifi-therm@1 { + reg = <1>; + io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pm8150_gpios { gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; gpio-line-names = @@ -566,6 +670,25 @@ &pm8150_gpios { "GPIO_10_P"; /* Green LED */ }; +&pm8150b_adc { + conn-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_adc_tm { + status = "okay"; + + conn-therm@0 { + reg = <0>; + io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pm8150b_gpios { gpio-line-names = "NC", @@ -582,6 +705,38 @@ &pm8150b_gpios { "NC"; }; +&pm8150l_adc { + skin-msm-therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pm8150l-therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + status = "okay"; + + skin-msm-therm@0 { + reg = <0>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pm8150l-therm@1 { + reg = <1>; + io-channels = <&pm8150l_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pm8150l_gpios { gpio-line-names = "NC", From e49c2912dbfa81cbe62849e4695f967f81c9350c Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Thu, 21 Jan 2021 01:01:39 -0800 Subject: [PATCH 043/100] arm64: dts: qcom: sdm630: add ICE registers and clocks Add the registers and clock for the Inline Crypto Engine (ICE) to the device tree node for the sdhci-msm host controller on sdm630. This allows sdhci-msm to support inline encryption on sdm630. Signed-off-by: Eric Biggers Link: https://lore.kernel.org/r/20210121090140.326380-9-ebiggers@kernel.org [bjorn: Changed indentation] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 37d5cc32f6b6..f91a928466c3 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -808,17 +808,19 @@ spmi_bus: spmi@800f000 { sdhc_1: sdhci@c0c4000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c0c4000 0x1000>, - <0x0c0c5000 0x1000>; - reg-names = "hc", "cqhci"; + <0x0c0c5000 0x1000>, + <0x0c0c8000 0x8000>; + reg-names = "hc", "cqhci", "ice"; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "xo", "ice"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; From 3a786086c6f8d226bf8be16d5b6d77ce51e6686b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 18 Jan 2021 10:40:05 +0530 Subject: [PATCH 044/100] arm64: dts: qcom: Add missing "-thermal" suffix for thermal zones The thermal devicetree binding requires the "-thermal" suffix for all thermal zones. Hence, add the missing suffix for PMIC based thermal zones. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210118051005.55958-8-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8150b.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8150l.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 15e87153a194..bdc76d504b78 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -11,7 +11,7 @@ / { thermal-zones { - pm8150 { + pm8150-thermal { polling-delay-passive = <100>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 8e2f3250c914..b21e56a46145 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -10,7 +10,7 @@ / { thermal-zones { - pm8150b { + pm8150b-thermal { polling-delay-passive = <100>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 9f214ceec2b7..52f094a2b713 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -10,7 +10,7 @@ / { thermal-zones { - pm8150l { + pm8150l-thermal { polling-delay-passive = <100>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 5ffdf37d8e31..91fff1f209e0 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -6,7 +6,7 @@ / { thermal-zones { - pm8994 { + pm8994-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 67283d60e2ac..6f5bb6b37ec2 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -9,7 +9,7 @@ / { thermal-zones { - pm8998 { + pm8998-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index ff4005186895..172be177fc8f 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pms405 { + pms405-thermal { polling-delay-passive = <250>; polling-delay = <1000>; From 0f7273c3daff285e581cb30f8dad9d086ea201b7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:19:42 +0100 Subject: [PATCH 045/100] arm64: dts: qcom: msm8992/4: Add RPM Power Domains Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118161943.105733-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 30 +++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8994.dtsi | 30 +++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 0c422af47917..c33b40db0f49 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -4,6 +4,7 @@ #include #include +#include / { interrupt-parent = <&intc>; @@ -713,6 +714,35 @@ rpmcc: rpmcc { compatible = "qcom,rpmcc-msm8992"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,msm8994-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 6e083a2f690b..9755780b53d7 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -4,6 +4,7 @@ #include #include +#include / { interrupt-parent = <&intc>; @@ -192,6 +193,35 @@ rpmcc: rpmcc { compatible = "qcom,rpmcc-msm8994"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,msm8994-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; }; }; }; From 72b312411de71887c3c0076017455d911b92bb18 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:21 +0100 Subject: [PATCH 046/100] arm64: dts: qcom: Add support for remaining Sony Kitakami boards This patch adds support for the following Xperias: * Z3+ [aka Z4 in some regions] (Ivy) * Z4 Tablet (Karin) * Z4 Tablet Wi-Fi (Karin_windy) [APQ8094] * Z5 Compact (Suzuran) * Z5 Premium (Satsuki) These devices are very similar in terms of hardware, with main differences being display panels. While at it, update comments describing hardware used: SMB charger seems to not be used after all, PMI8994 charger is in use instead. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 5 +++++ ...q8094-sony-xperia-kitakami-karin_windy.dts | 20 ++++++++++++++++++ .../qcom/msm8994-sony-xperia-kitakami-ivy.dts | 13 ++++++++++++ .../msm8994-sony-xperia-kitakami-karin.dts | 21 +++++++++++++++++++ .../msm8994-sony-xperia-kitakami-satsuki.dts | 13 ++++++++++++ .../msm8994-sony-xperia-kitakami-suzuran.dts | 13 ++++++++++++ .../qcom/msm8994-sony-xperia-kitakami.dtsi | 15 ++++++++++--- 7 files changed, 97 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b5d86739f781..59455db7b493 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb @@ -14,7 +15,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-cityman.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts b/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts new file mode 100644 index 000000000000..60497457a555 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +/* As the names may imply, there is quite a bunch of duplication there. */ +#include "msm8994-sony-xperia-kitakami-karin.dts" + +/ { + model = "Sony Xperia Z4 Tablet (Wi-Fi)"; + compatible = "sony,karin_windy", "qcom,apq8094"; + + /* + * This model uses the APQ variant of MSM8994 (APQ8094). + * The v1/v2/v2.1 story (from kitakami.dtsi) also applies here. + */ + qcom,msm-id = <253 0x20000>, <253 0x20001>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts new file mode 100644 index 000000000000..4c7a90987f08 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8994-sony-xperia-kitakami.dtsi" + +/ { + model = "Sony Xperia Z3+/Z4"; + compatible = "sony,ivy-row", "qcom,msm8994"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts new file mode 100644 index 000000000000..7e657861387b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8994-sony-xperia-kitakami.dtsi" + +/ { + model = "Sony Xperia Z4 Tablet (LTE)"; + compatible = "sony,karin-row", "qcom,msm8994"; +}; + +&blsp_i2c5 { + /* + * TI LP8557 backlight driver @ 2c + * AD AD7146 touch controller @ 2f + * sii8620 HDMI/MHL bridge @ 72 (kitakami-common) + */ +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts new file mode 100644 index 000000000000..1081fe6a4d67 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8994-sony-xperia-kitakami.dtsi" + +/ { + model = "Sony Xperia Z5 Premium"; + compatible = "sony,satsuki-row", "qcom,msm8994"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts new file mode 100644 index 000000000000..2c670ab28613 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8994-sony-xperia-kitakami.dtsi" + +/ { + model = "Sony Xperia Z5 Compact"; + compatible = "sony,suzuran-row", "qcom,msm8994"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 791f254ac3f8..71d7187eb090 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -11,8 +11,17 @@ / { /* required for bootloader to select correct board */ - qcom,msm-id = <0xcf 0x20001>; + + /* + * We support MSM8994 v2 (0x20000) and v2.1 (0x20001). + * The V1 chip (0x0 and 0x10000) is significantly different + * and requires driver-side changes (including CPR, be warned!!). + * Besides that, it's very rare. + */ + qcom,msm-id = <207 0x20000>, <207 0x20001>; + /* We only use pm8994+pmi8994. */ qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>; + /* This property is shared across all kitakami devices. */ qcom,board-id = <8 0>; /* Kitakami firmware doesn't support PSCI */ @@ -120,7 +129,7 @@ &blsp_spi0 { &blsp_i2c2 { status = "okay"; - /* NXP NFC */ + /* NXP PN547 NFC */ }; &blsp_i2c4 { @@ -132,7 +141,7 @@ &blsp_i2c4 { &blsp_i2c5 { status = "okay"; - /* SMB1357 charger and sii8620 HDMI/MHL bridge */ + /* sii8620 HDMI/MHL bridge */ }; &blsp_i2c6 { From 1628dfe5f67ea8e9be005ece9a0bfdb75a05b214 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:22 +0100 Subject: [PATCH 047/100] arm64: dts: qcom: msm8992-bullhead: Update regulator config * Include pm(i)8994 dtsi * Add PMI8994 RPM regulators * Add comments concerning "missing" regulators Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8992-bullhead-rev-101.dts | 39 +++++++++++++------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts index 5969b5cfdc85..cacbfdbd69e3 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "msm8992.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" / { model = "LG Nexus 5X"; @@ -44,7 +46,7 @@ &blsp1_uart2 { }; &rpm_requests { - pm8994-regulators { + pm8994_regulators: pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; vdd_l1-supply = <&pm8994_s1>; @@ -53,15 +55,17 @@ pm8994-regulators { vdd_l4_27_31-supply = <&pm8994_s3>; vdd_l5_7-supply = <&pm8994_s3>; vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vreg_vph_pwr>; - vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; - vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; + vdd_l8_16_30-supply = <&vph_pwr>; + vdd_l9_10_18_22-supply = <&vph_pwr>; + vdd_l13_19_23_24-supply = <&vph_pwr>; vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vreg_vph_pwr>; - vdd_l20_21-supply = <&vreg_vph_pwr>; + vdd_l17_29-supply = <&vph_pwr>; + vdd_l20_21-supply = <&vph_pwr>; vdd_l25-supply = <&pm8994_s5>; vdd_lvs1_2 = <&pm8994_s4>; + /* S1, S2, S6 and S12 are managed by RPMPD */ + pm8994_s1: s1 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; @@ -93,6 +97,8 @@ pm8994_s7: s7 { regulator-max-microvolt = <1000000>; }; + /* S8, S9, S10 and S11 - SPMI-managed VDD_APC */ + pm8994_l1: l1 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -113,18 +119,14 @@ pm8994_l4: l4 { regulator-max-microvolt = <1225000>; }; - pm8994_l5: l5 { - /* TODO */ - }; + /* L5 is inaccessible from RPM */ pm8994_l6: l6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - pm8994_l7: l7 { - /* TODO */ - }; + /* L7 is inaccessible from RPM */ pm8994_l8: l8 { regulator-min-microvolt = <1800000>; @@ -266,6 +268,19 @@ pm8994_l32: l32 { */ }; }; + + pmi8994_regulators: pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + pmi8994_s1: s1 {}; + + /* S2 & S3 - VDD_GFX */ + + pmi8994_bby: boost-bypass {}; + }; }; &sdhc_1 { From 31d9dbd2ae36a368e2e20ade76db16c6c489735f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:23 +0100 Subject: [PATCH 048/100] arm64: dts: qcom: msm8992-libra: Update regulator config * Add PMI8994 RPM regulators * Add missing PM8994 LVSes * Add comments concerning "missing" regulators Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8992-xiaomi-libra.dts | 53 +++++++++++-------- 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 4f64ca3ea1ef..5dab8ee0c7d3 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -144,24 +144,16 @@ pm8994-regulators { vdd_l4_27_31-supply = <&pm8994_s3>; vdd_l5_7-supply = <&pm8994_s3>; vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vreg_vph_pwr>; - vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; - vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; + vdd_l8_16_30-supply = <&vph_pwr>; + vdd_l9_10_18_22-supply = <&vph_pwr>; + vdd_l13_19_23_24-supply = <&vph_pwr>; vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vreg_vph_pwr>; - vdd_l20_21-supply = <&vreg_vph_pwr>; + vdd_l17_29-supply = <&vph_pwr>; + vdd_l20_21-supply = <&vph_pwr>; vdd_l25-supply = <&pm8994_s5>; vdd_lvs1_2 = <&pm8994_s4>; - pm8994_s1: s1 { - /* unused */ - status = "disabled"; - }; - - pm8994_s2: s2 { - /* unused */ - status = "disabled"; - }; + /* S1, S2, S6 and S12 are managed by RPMPD */ pm8994_s3: s3 { regulator-min-microvolt = <1300000>; @@ -186,6 +178,8 @@ pm8994_s7: s7 { regulator-max-microvolt = <1000000>; }; + /* S8, S9, S10 and S11 - SPMI-managed VDD_APC */ + pm8994_l1: l1 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -206,20 +200,14 @@ pm8994_l4: l4 { regulator-max-microvolt = <1225000>; }; - pm8994_l5: l5 { - /* unused */ - status = "disabled"; - }; + /* L5 is inaccessible from RPM */ pm8994_l6: l6 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - pm8994_l7: l7 { - /* unused */ - status = "disabled"; - }; + /* L7 is inaccessible from RPM */ pm8994_l8: l8 { regulator-min-microvolt = <1800000>; @@ -352,6 +340,27 @@ pm8994_l32: l32 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + pm8994_lvs1: lvs1 {}; + pm8994_lvs2: lvs2 {}; + }; + + pmi8994_regulators: pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + vdd_s1-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + pmi8994_s1: s1 { + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + + /* S2 & S3 - VDD_GFX */ + + pmi8994_bby: boost-bypass { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3600000>; + }; }; }; From 53364cfcaa7d20d9b066f546d0bee994310fc972 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:24 +0100 Subject: [PATCH 049/100] arm64: dts: qcom: msm8992/4: Rename vreg_vph_pwr to vph_pwr Rename the fixed regulator to follow the common naming scheme Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 ++--- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index c33b40db0f49..b2046497dcaa 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -755,10 +755,9 @@ timer { ; }; - vreg_vph_pwr: vreg-vph-pwr { + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; - status = "okay"; - regulator-name = "vph-pwr"; + regulator-name = "vph_pwr"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 9755780b53d7..2a6596406d9b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -820,9 +820,9 @@ timer { ; }; - vreg_vph_pwr: vreg-vph-pwr { + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; - regulator-name = "vph-pwr"; + regulator-name = "vph_pwr"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; From 676b61b4790ad60512b35dbda8f9f6f83c5642dc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:25 +0100 Subject: [PATCH 050/100] arm64: dts: qcom: msm/apq8994-kitakami: Add regulator config Add regulator config for all Kitakami devices, commonizing where applicable. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- ...q8094-sony-xperia-kitakami-karin_windy.dts | 3 + .../qcom/msm8994-sony-xperia-kitakami-ivy.dts | 13 + .../msm8994-sony-xperia-kitakami-karin.dts | 22 ++ .../msm8994-sony-xperia-kitakami-satsuki.dts | 5 + .../msm8994-sony-xperia-kitakami-sumire.dts | 2 + .../msm8994-sony-xperia-kitakami-suzuran.dts | 7 + .../qcom/msm8994-sony-xperia-kitakami.dtsi | 300 ++++++++++++++---- 7 files changed, 295 insertions(+), 57 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts b/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts index 60497457a555..a8dffc8c64ea 100644 --- a/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts +++ b/arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dts @@ -18,3 +18,6 @@ / { */ qcom,msm-id = <253 0x20000>, <253 0x20001>; }; + +/delete-node/ &pm8994_l1; +/delete-node/ &pm8994_l19; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts index 4c7a90987f08..b5e90c85aaf6 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dts @@ -11,3 +11,16 @@ / { model = "Sony Xperia Z3+/Z4"; compatible = "sony,ivy-row", "qcom,msm8994"; }; + +&pm8994_l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; +}; + +&pm8994_l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; +}; + +/delete-node/ &pm8994_l19; +/delete-node/ &pm8994_l32; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts index 7e657861387b..743a2a076552 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts @@ -19,3 +19,25 @@ &blsp_i2c5 { * sii8620 HDMI/MHL bridge @ 72 (kitakami-common) */ }; + +&pm8994_l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; +}; + +&pm8994_l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; +}; + +&pm8994_l22 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; +}; + +&pm8994_l25 { + regulator-min-microvolt = <1037500>; + regulator-max-microvolt = <1037500>; +}; + +/delete-node/ &pm8994_l32; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts index 1081fe6a4d67..1385956a69f3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dts @@ -11,3 +11,8 @@ / { model = "Sony Xperia Z5 Premium"; compatible = "sony,satsuki-row", "qcom,msm8994"; }; + +&pm8994_l14 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts index 5d6bbbf6c119..868a2c9d6496 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts @@ -11,3 +11,5 @@ / { model = "Sony Xperia Z5"; compatible = "sony,sumire-row", "qcom,msm8994"; }; + +/delete-node/ &pm8994_l19; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts index 2c670ab28613..f129479bbf95 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dts @@ -11,3 +11,10 @@ / { model = "Sony Xperia Z5 Compact"; compatible = "sony,suzuran-row", "qcom,msm8994"; }; + +&pm8994_l14 { + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; +}; + +/delete-node/ &pm8994_l19; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 71d7187eb090..e31c31c2b936 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -161,59 +161,233 @@ &blsp2_uart2 { &rpm_requests { pm8994_regulators: pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; - vdd_l1-supply = <&pm8994_s1>; - vdd_l2_26_28-supply = <&pm8994_s3>; - vdd_l3_11-supply = <&pm8994_s3>; - vdd_l4_27_31-supply = <&pm8994_s3>; - vdd_l5_7-supply = <&pm8994_s3>; - vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vreg_vph_pwr>; - vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; - vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; - vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vreg_vph_pwr>; - vdd_l20_21-supply = <&vreg_vph_pwr>; - vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; - pm8994_s1: s1 {}; - pm8994_s2: s2 {}; - pm8994_s3: s3 {}; - pm8994_s4: s4 {}; - pm8994_s5: s5 {}; - pm8994_s6: s6 {}; - pm8994_s7: s7 {}; + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_l1-supply = <&pmi8994_s1>; + vdd_l2_l26_l28-supply = <&pm8994_s3>; + vdd_l3_l11-supply = <&pm8994_s3>; + vdd_l4_l27_l31-supply = <&pm8994_s3>; + vdd_l5_l7-supply = <&pm8994_s5>; + vdd_l6_l12_l32-supply = <&pm8994_s5>; + vdd_l8_l16_l30-supply = <&vph_pwr>; + vdd_l9_l10_l18_l22-supply = <&pmi8994_bby>; + vdd_l13_l19_l23_l24-supply = <&pmi8994_bby>; + vdd_l14_l15-supply = <&pm8994_s5>; + vdd_l17_l29-supply = <&pmi8994_bby>; + vdd_l20_l21-supply = <&pmi8994_bby>; + vdd_l25-supply = <&pm8994_s3>; + vdd_lvs1_lvs2-supply = <&pm8994_s4>; - pm8994_l1: l1 {}; - pm8994_l2: l2 {}; - pm8994_l3: l3 {}; - pm8994_l4: l4 {}; - pm8994_l6: l6 {}; - pm8994_l8: l8 {}; - pm8994_l9: l9 {}; - pm8994_l10: l10 {}; - pm8994_l11: l11 {}; - pm8994_l12: l12 {}; - pm8994_l13: l13 {}; - pm8994_l14: l14 {}; - pm8994_l15: l15 {}; - pm8994_l16: l16 {}; - pm8994_l17: l17 {}; - pm8994_l18: l18 {}; - pm8994_l19: l19 {}; - pm8994_l20: l20 {}; - pm8994_l21: l21 {}; - pm8994_l22: l22 {}; - pm8994_l23: l23 {}; - pm8994_l24: l24 {}; - pm8994_l25: l25 {}; - pm8994_l26: l26 {}; - pm8994_l27: l27 {}; - pm8994_l28: l28 {}; - pm8994_l29: l29 {}; - pm8994_l30: l30 {}; - pm8994_l31: l31 {}; - pm8994_l32: l32 {}; + /* S1, S2, S6 and S12 are managed by RPMPD */ + + pm8994_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8994_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-always-on; + regulator-system-load = <325000>; + }; + + pm8994_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pm8994_s7: s7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + /* + * S8 - SPMI-managed VDD_APC0 + * S9, S10 and S11 (the main one) - SPMI-managed VDD_APC1 + */ + + pm8994_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l2: l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-allow-set-load; + regulator-system-load = <10000>; + }; + + pm8994_l3: l3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + pm8994_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + /* L5 is inaccessible from RPM */ + + pm8994_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* L7 is inaccessible from RPM */ + + pm8994_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l11: l11 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-system-load = <10000>; + }; + + pm8994_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8994_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-system-load = <10000>; + }; + + pm8994_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l17: l17 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + }; + + pm8994_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8994_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8994_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-system-load = <570000>; + }; + + pm8994_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + }; + + pm8994_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8994_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8994_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3150000>; + }; + + pm8994_l25: l25 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l26: l26 { + regulator-min-microvolt = <987500>; + regulator-max-microvolt = <987500>; + }; + + pm8994_l27: l27 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l28: l28 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-allow-set-load; + regulator-system-load = <10000>; + }; + + pm8994_l29: l29 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l30: l30 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l31: l31 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + regulator-system-load = <10000>; + }; + + pm8994_l32: l32 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; pm8994_lvs1: lvs1 {}; pm8994_lvs2: lvs2 {}; @@ -222,22 +396,34 @@ pm8994_regulators: pm8994-regulators { pmi8994_regulators: pmi8994-regulators { compatible = "qcom,rpm-pmi8994-regulators"; - pmi8994_s1: s1 {}; - pmi8994_s2: s2 {}; - pmi8994_s3: s3 {}; - pmi8994_bby: boost-bypass {}; + vdd_s1-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + pmi8994_s1: s1 { + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + + /* S2 & S3 - VDD_GFX */ + + pmi8994_bby: boost-bypass { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3600000>; + }; }; }; &sdhc1 { - /* There is an issue with the eMMC causing permanent + /* + * There is an issue with the eMMC causing permanent * damage to the card if a quirk isn't addressed. * Until it's fixed, disable the MMC so as not to brick * devices. */ status = "disabled"; - /* Downstream pushes 2.95V to the sdhci device, + /* + * Downstream pushes 2.95V to the sdhci device, * but upstream driver REALLY wants to make vmmc 1.8v * cause of the hs400-1_8v mode. MMC works fine without * that regulator, so let's not use it for now. From e8528157b7f0bc20dd63867f4946dc5b5195527b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:26 +0100 Subject: [PATCH 051/100] arm64: dts: qcom: msm8994-kitakami: Add Synaptics RMI touchscreen All Kitakami phones use Synaptics RMI4 touchscreens attached to the same i2c bus. Configure and enable it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../msm8994-sony-xperia-kitakami-karin.dts | 2 + .../qcom/msm8994-sony-xperia-kitakami.dtsi | 45 ++++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts index 743a2a076552..4dcf42eafb3a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts @@ -41,3 +41,5 @@ &pm8994_l25 { }; /delete-node/ &pm8994_l32; +/* Z4 tablets use a different touchscreen. */ +/delete-node/ &touchscreen; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index e31c31c2b936..33af174b78ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -147,7 +147,34 @@ &blsp_i2c5 { &blsp_i2c6 { status = "okay"; - /* Synaptics touchscreen */ + touchscreen: rmi4-i2c-dev@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + + vdd-supply = <&pm8994_l22>; + vio-supply = <&pm8994_s4>; + + syna,reset-delay-ms = <220>; + syna,startup-delay-ms = <220>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; }; &blsp1_uart2 { @@ -433,3 +460,19 @@ &sdhc1 { * vqmmc-supply = <&pm8994_s4>; */ }; + +&tlmm { + ts_int_active: ts-int-active { + pins = "gpio42"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + ts_reset_active: ts-reset-active { + pins = "gpio109"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; From ab8e4a853731b37297914712b315a9fd6bbee366 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:27 +0100 Subject: [PATCH 052/100] arm64: dts: qcom: msm8994-kitakami: Add uSD card support Assign regulators and enable regulator-set-load on VMMC so as to provide sufficient power. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-7-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 33af174b78ab..26b54f360fc3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -355,6 +355,8 @@ pm8994_l21: l21 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <800000>; }; pm8994_l22: l22 { @@ -461,6 +463,14 @@ &sdhc1 { */ }; +&sdhc2 { + status = "okay"; + + cd-gpios = <&tlmm 100 0>; + vmmc-supply = <&pm8994_l21>; + vqmmc-supply = <&pm8994_l13>; +}; + &tlmm { ts_int_active: ts-int-active { pins = "gpio42"; From e9783584c9b7edc8726b4e8858009028d98850f9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:28 +0100 Subject: [PATCH 053/100] arm64: dts: qcom: msm8994-kitakami: Add VDD_GFX regulator This is required for the GPU to function. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-8-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 26b54f360fc3..05155859cf6a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -185,6 +185,24 @@ &blsp2_uart2 { status = "okay"; }; +&pmi8994_spmi_regulators { + /* + * Yeah, this one *is* managed by RPMPD, but also needs + * to be hacked up as a-o due to the GPU device only accepting a single + * power domain.. which still isn't enough and forces us to bind + * OXILI_CX and OXILI_GX together! + */ + vdd_gfx: s2@1700 { + reg = <0x1700 0x100>; + regulator-name = "VDD_GFX"; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + + /* hack until we rig up the gpu consumer */ + regulator-always-on; + }; +}; + &rpm_requests { pm8994_regulators: pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; From a046032c37c055757916e36ba3f3a90540d65152 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:29 +0100 Subject: [PATCH 054/100] arm64: dts: qcom: msm8994: Fix BLSP2_UART2 node Fix up the node to make the peripheral functional. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-9-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 2a6596406d9b..592e18f4628f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -523,7 +523,7 @@ blsp_i2c6: i2c@f9928000 { blsp2_uart2: serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; - interrupts = ; + interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; @@ -618,16 +618,18 @@ blsp1_uart2_sleep: blsp1-uart2-sleep { blsp2_uart2_default: blsp2-uart2-default { function = "blsp_uart8"; - pins = "gpio45", "gpio46"; - drive-strength = <2>; + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + drive-strength = <16>; bias-disable; }; blsp2_uart2_sleep: blsp2-uart2-sleep { function = "gpio"; - pins = "gpio45", "gpio46"; + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; drive-strength = <2>; - bias-pull-down; + bias-disable; }; i2c1_default: i2c1-default { From 74d6d0a145835bf59fc37e87ea36a22ecaf611be Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:30 +0100 Subject: [PATCH 055/100] arm64: dts: qcom: msm8994/8994-kitakami: Fix up the memory map The previous map was wrong. Fix it up. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-10-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 49 +++++++------------ arch/arm64/boot/dts/qcom/msm8994.dtsi | 45 ++++++++++++++++- 2 files changed, 62 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 05155859cf6a..e962fc5f8b1b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -72,47 +72,23 @@ button@3 { }; reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - /* This is for getting crash logs using Android downstream kernels */ ramoops@1fe00000 { compatible = "ramoops"; - reg = <0x0 0x1fe00000 0x0 0x200000>; + reg = <0 0x1fe00000 0 0x200000>; console-size = <0x100000>; record-size = <0x10000>; ftrace-size = <0x10000>; pmsg-size = <0x80000>; }; - continuous_splash: framebuffer@3401000{ - reg = <0x0 0x3401000 0x0 0x2200000>; - no-map; - }; - - dfps_data_mem: dfps_data_mem@3400000 { - reg = <0x0 0x3400000 0x0 0x1000>; - no-map; - }; - - peripheral_region: peripheral_region@7400000 { - reg = <0x0 0x7400000 0x0 0x1c00000>; - no-map; - }; - - modem_region: modem_region@9000000 { - reg = <0x0 0x9000000 0x0 0x5a00000>; - no-map; - }; - - tzapp: modem_region@ea00000 { - reg = <0x0 0xea00000 0x0 0x1900000>; - no-map; - }; - fb_region: fb_region@40000000 { - reg = <0x00 0x40000000 0x00 0x1000000>; + reg = <0 0x40000000 0 0x1000000>; + no-map; + }; + + tzapp: memory@c7800000 { + reg = <0 0xc7800000 0 0x1900000>; no-map; }; }; @@ -185,6 +161,17 @@ &blsp2_uart2 { status = "okay"; }; +/* + * Kitakami bootloader only turns cont_splash on when it detects + * specific downstream MDSS/backlight nodes in the active DTB. + * One way to use that framebuffer is to load a secondary instance of + * LK with the downstream DTB appended and then, only from there, load + * mainline Linux. + */ +&cont_splash_mem { + reg = <0 0x3401000 0 0x2200000>; +}; + &pmi8994_spmi_regulators { /* * Yeah, this one *is* managed by RPMPD, but also needs diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 592e18f4628f..e694aaad3c99 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -170,8 +170,51 @@ reserved-memory { #size-cells = <2>; ranges; + dfps_data_mem: dfps_data_mem@3400000 { + reg = <0 0x03400000 0 0x1000>; + no-map; + }; + + cont_splash_mem: memory@3800000 { + reg = <0 0x03800000 0 0x2400000>; + no-map; + }; + smem_mem: smem_region@6a00000 { - reg = <0x0 0x6a00000 0x0 0x200000>; + reg = <0 0x06a00000 0 0x200000>; + no-map; + }; + + mpss_mem: memory@7000000 { + reg = <0 0x07000000 0 0x5a00000>; + no-map; + }; + + peripheral_region: memory@ca00000 { + reg = <0 0x0ca00000 0 0x1f00000>; + no-map; + }; + + rmtfs_mem: memory@c6400000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xc6400000 0 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + + mba_mem: memory@c6700000 { + reg = <0 0xc6700000 0 0x100000>; + no-map; + }; + + audio_mem: memory@c7000000 { + reg = <0 0xc7000000 0 0x800000>; + no-map; + }; + + adsp_mem: memory@c9400000 { + reg = <0 0xc9400000 0 0x3f00000>; no-map; }; }; From 54b1511e4f31e8f849ebbf91be025c9800e0c60d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 Jan 2021 17:24:31 +0100 Subject: [PATCH 056/100] arm64: dts: qcom: msm8994-kitakami: Add missing email in the copyright I forgot to do this the first time around. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210118162432.107275-11-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts | 2 +- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts index 868a2c9d6496..d3ba9867a369 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Konrad Dybcio */ /dts-v1/; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index e962fc5f8b1b..586d866188d7 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Konrad Dybcio */ #include "msm8994.dtsi" From 28cc13e4060c62e87936bcbfd7a1313383d2a6d3 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 26 Jan 2021 21:17:29 +0530 Subject: [PATCH 057/100] arm64: dts: qcom: sc7180: Add watchdog bark interrupt Specify bark interrupt for APSS watchdog to support pre-timeout notification on SC7180 SoC. Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/535b368f6c22bab7078842d803a73e695f28a751.1611466260.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 2bd06beafecc..04445cd3cfd9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3349,6 +3349,7 @@ watchdog@17c10000 { compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; + interrupts = ; }; timer@17c20000{ From 36c436b03c584ad9ecd7820ccdc4ae5ad76d79aa Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 26 Jan 2021 21:17:30 +0530 Subject: [PATCH 058/100] arm64: dts: qcom: sdm845: Add watchdog bark interrupt Specify bark interrupt for APSS watchdog to support pre-timeout notification on SDM845 SoC. Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/7740e8ef57361d33da64e823b2356da2be0065b8.1611466260.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bcf888381f14..2da77e16f1b3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4573,6 +4573,7 @@ watchdog@17980000 { compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; reg = <0 0x17980000 0 0x1000>; clocks = <&sleep_clk>; + interrupts = ; }; apss_shared: mailbox@17990000 { From b094c8f8dd2a01d5b537f68d41e6ef201de73259 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 26 Jan 2021 21:17:31 +0530 Subject: [PATCH 059/100] arm64: dts: qcom: sm8150: Add watchdog bark interrupt Specify bark interrupt for APSS watchdog to support pre-timeout notification on SM8150 SoC. Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/02700a5ac413bf5a7e3a0102233d1d64b47bb2cf.1611466260.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 9a939c6095ea..e5bb17bc2f46 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1975,6 +1975,7 @@ watchdog@17c10000 { compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; + interrupts = ; }; timer@17c20000 { From 46a4359f9156f584bf5b17b8220ab6c59e861963 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 26 Jan 2021 21:17:32 +0530 Subject: [PATCH 060/100] arm64: dts: qcom: sm8250: Add watchdog bark interrupt Specify bark interrupt for APSS watchdog to support pre-timeout notification on SM8250 SoC. Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/ff0758b158d62e82fd0636f5861115f435f821ac.1611466260.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 20e70d5641ea..61191f7f5861 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3289,6 +3289,7 @@ watchdog@17c10000 { compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; + interrupts = ; }; timer@17c20000 { From bd67534d18b4a1ca8755f59702d4acf5a9ba7b1a Mon Sep 17 00:00:00 2001 From: Vincent Knecht Date: Sat, 30 Jan 2021 11:57:10 +0100 Subject: [PATCH 061/100] dt-bindings: vendor-prefixes: add Alcatel Document vendor prefix for Alcatel Signed-off-by: Vincent Knecht Link: https://lore.kernel.org/r/20210130105717.2628781-2-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 041ae90b0d8f..08150a1217e9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -59,6 +59,8 @@ patternProperties: description: Aeroflex Gaisler AB "^al,.*": description: Annapurna Labs + "^alcatel,.*": + description: Alcatel "^allegro,.*": description: Allegro DVT "^allo,.*": From b32155ff0256dbc053874e61f532a75fdfb5ec31 Mon Sep 17 00:00:00 2001 From: Vincent Knecht Date: Sat, 30 Jan 2021 11:57:11 +0100 Subject: [PATCH 062/100] arm64: dts: qcom: Add device tree for Alcatel Idol 3 (4.7") The Alcatel Idol 3 (4.7") is a smartphone based on MSM8916. Add a device tree with support for USB, eMMC, SD-Card, WiFi, BT, power/volume buttons, vibrator and the following sensors: magnetometer, accelerometer, gyroscope, ambient light+proximity Reviewed-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Vincent Knecht Link: https://lore.kernel.org/r/20210130105717.2628781-3-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 291 ++++++++++++++++++ 2 files changed, 292 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 59455db7b493..0feeedb712cc 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts new file mode 100644 index 000000000000..540b1fa4b260 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include + +/ { + model = "Alcatel OneTouch Idol 3 (4.7)"; + compatible = "alcatel,idol347", "qcom,msm8916"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 69 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp_i2c5 { + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + vdd-supply = <&pm8916_l17>; + vid-supply = <&pm8916_l6>; + reset-gpios = <&msmgpio 8 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mag_reset_default>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + + accelerometer@f { + compatible = "kionix,kxtj21009"; + reg = <0x0f>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + interrupt-parent = <&msmgpio>; + interrupts = <31 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_int_default>; + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + + proximity@48 { + compatible = "sensortek,stk3310"; + reg = <0x48>; + interrupt-parent = <&msmgpio>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&proximity_int_default>; + }; + + gyroscope@68 { + compatible = "bosch,bmg160"; + reg = <0x68>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + interrupt-parent = <&msmgpio>; + interrupts = <97 IRQ_TYPE_EDGE_RISING>, + <98 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gyro_int_default>; + }; +}; + +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + accel_int_default: accel-int-default { + pins = "gpio31"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + gyro_int_default: gyro-int-default { + pins = "gpio97", "gpio98"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + mag_reset_default: mag-reset-default { + pins = "gpio8"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + proximity_int_default: proximity-int-default { + pins = "gpio12"; + function = "gpio"; + + drive-strength = <6>; + bias-pull-up; + }; + + usb_id_default: usb-id-default { + pins = "gpio69"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; From 5f36d633c214bc21eaa7590d96e6a425261ccd57 Mon Sep 17 00:00:00 2001 From: Vincent Knecht Date: Sat, 30 Jan 2021 11:57:12 +0100 Subject: [PATCH 063/100] arm64: dts: qcom: Disable MDSS by default for 8916/8016 devices Disable MDSS (Mobile Display Subsystem) by default in msm8916.dtsi and only explicitly enable it in devices' DT which actually use it. This leads to faster boot and cleaner logs for other devices, which also won't have to explicitly disable MDSS to use framebuffer. Reviewed-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Vincent Knecht Link: https://lore.kernel.org/r/20210130105717.2628781-4-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + 3 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 3a9538e1ec97..6aef0c2e4f0a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -301,6 +301,10 @@ &lpass { status = "okay"; }; +&mdss { + status = "okay"; +}; + &pm8916_resin { status = "okay"; linux,code = ; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index f1af798abd74..230ba3ce3277 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -132,6 +132,10 @@ &dsi0 { pinctrl-1 = <&mdss_sleep>; }; +&mdss { + status = "okay"; +}; + &pm8916_resin { status = "okay"; linux,code = ; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 402e891a84ab..8f9a651d3827 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -913,6 +913,7 @@ tcsr: syscon@1937000 { }; mdss: mdss@1a00000 { + status = "disabled"; compatible = "qcom,mdss"; reg = <0x01a00000 0x1000>, <0x01ac8000 0x3000>; From 2c1b8ebe929f1d452c95f8a4d32e3a265eb5b2c2 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 27 Jan 2021 18:00:49 +0530 Subject: [PATCH 064/100] dt-bindings: arm: qcom: Document SM8350 SoC and boards Document the SM8350 SoC binding and also the boards using it. Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210127123054.263231-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c97d4a580f47..8fe7e473bfdf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -41,6 +41,7 @@ description: | sdm660 sdm845 sm8250 + sm8350 The 'board' element must be one of the following strings: @@ -178,6 +179,11 @@ properties: - qcom,sm8250-mtp - const: qcom,sm8250 + - items: + - enum: + - qcom,sm8350-mtp + - const: qcom,sm8350 + additionalProperties: true ... From 8767fe36d90e3433bd18eb0f84d852da73d5c8c6 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 27 Jan 2021 18:00:51 +0530 Subject: [PATCH 065/100] dt-bindings: arm: cpus: Add kryo685 compatible Kryo685 is found in SM8350, so add it to the list of cpu compatibles Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210127123054.263231-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 14cd727d3c4b..3a0b4c54cd8e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -169,6 +169,7 @@ properties: - qcom,kryo385 - qcom,kryo468 - qcom,kryo485 + - qcom,kryo685 - qcom,scorpion enable-method: From 80ad7f3349e63a12b9b9ba767884a513df362ec2 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 27 Jan 2021 18:00:52 +0530 Subject: [PATCH 066/100] dt-bindings: firmware: scm: Add SM8250 and SM8350 compatible Add compatible for SM8150 and SM8350 SoCs. Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210127123054.263231-5-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 78456437df5f..a884955f861e 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -22,6 +22,8 @@ Required properties: * "qcom,scm-sc7180" * "qcom,scm-sdm845" * "qcom,scm-sm8150" + * "qcom,scm-sm8250" + * "qcom,scm-sm8350" and: * "qcom,scm" - clocks: Specifies clocks needed by the SCM interface, if any: From b7e8f433a673eb875007111a75e9dbdc61ea5c14 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 27 Jan 2021 18:00:53 +0530 Subject: [PATCH 067/100] arm64: dts: qcom: Add basic devicetree support for SM8350 SoC Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC. This adds gcc, pinctrl, reserved memory, uart, cpu nodes for this SoC. Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210127123054.263231-6-vkoul@kernel.org [bjorn: Adjusted 4th timer interrupt, per input from Sai] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 499 +++++++++++++++++++++++++++ 1 file changed, 499 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi new file mode 100644 index 000000000000..5ef460458f5c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Linaro Limaited + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo685"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8350", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: memory@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + reserved_xbl_uefi_log: memory@80880000 { + reg = <0x0 0x80880000 0x0 0x14000>; + no-map; + }; + + smem_mem: memory@80900000 { + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + }; + + cpucp_fw_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0x4600000>; + no-map; + }; + + pil_camera_mem: mmeory@85200000 { + reg = <0x0 0x85200000 0x0 0x500000>; + no-map; + }; + + pil_video_mem: memory@85700000 { + reg = <0x0 0x85700000 0x0 0x500000>; + no-map; + }; + + pil_cvp_mem: memory@85c00000 { + reg = <0x0 0x85c00000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: memory@86100000 { + reg = <0x0 0x86100000 0x0 0x2100000>; + no-map; + }; + + pil_slpi_mem: memory@88200000 { + reg = <0x0 0x88200000 0x0 0x1500000>; + no-map; + }; + + pil_cdsp_mem: memory@89700000 { + reg = <0x0 0x89700000 0x0 0x1e00000>; + no-map; + }; + + pil_ipa_fw_mem: memory@8b500000 { + reg = <0x0 0x8b500000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@8b510000 { + reg = <0x0 0x8b510000 0x0 0xa000>; + no-map; + }; + + pil_gpu_mem: memory@8b51a000 { + reg = <0x0 0x8b51a000 0x0 0x2000>; + no-map; + }; + + pil_spss_mem: memory@8b600000 { + reg = <0x0 0x8b600000 0x0 0x100000>; + no-map; + }; + + pil_modem_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0x10000000>; + no-map; + }; + + hyp_reserved_mem: memory@d0000000 { + reg = <0x0 0xd0000000 0x0 0x800000>; + no-map; + }; + + pil_trustedvm_mem: memory@d0800000 { + reg = <0x0 0xd0800000 0x0 0x76f7000>; + no-map; + }; + + qrtr_shbuf: memory@d7ef7000 { + reg = <0x0 0xd7ef7000 0x0 0x9000>; + no-map; + }; + + chan0_shbuf: memory@d7f00000 { + reg = <0x0 0xd7f00000 0x0 0x80000>; + no-map; + }; + + chan1_shbuf: memory@d7f80000 { + reg = <0x0 0xd7f80000 0x0 0x80000>; + no-map; + }; + + removed_mem: memory@d8800000 { + reg = <0x0 0xd8800000 0x0 0x6800000>; + no-map; + }; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm8350"; + reg = <0x0 0x00100000 0x0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qupv3_id_1: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x009c0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc 121>, + <&gcc 122>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart2: serial@98c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0098c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc 83>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart3_default_state>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8350-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, + <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, + <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, + <156 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + aoss_qmp: qmp@c300000 { + compatible = "qcom,sm8350-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8350-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 203>; + + qup_uart3_default_state: qup-uart3-default-state { + rx { + pins = "gpio18"; + function = "qup3"; + }; + tx { + pins = "gpio19"; + function = "qup3"; + }; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + reg = <0x0 0x17c20000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17c21000 0x0 0x1000>, + <0x0 0x17c22000 0x0 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17c23000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17c25000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17c27000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17c29000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x17c2b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x17c2d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + rpmhcc: clock-controller { + compatible = "qcom,sm8350-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From 0684074a46e8ef939c7afe6b9c7381563599c33a Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Wed, 27 Jan 2021 18:00:54 +0530 Subject: [PATCH 068/100] arm64: dts: qcom: Add basic devicetree support for SM8350-MTP board Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC MTP board. This enabled uart node and adds rpmh-regulators present for this board. Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20210127123054.263231-7-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 250 ++++++++++++++++++++++++ 2 files changed, 251 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8350-mtp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0feeedb712cc..ac9a1b61aab1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -58,3 +58,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts new file mode 100644 index 000000000000..8923657579fb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Linaro Limited + */ + +/dts-v1/; + +#include +#include "sm8350.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sm8350 MTP"; + compatible = "qcom,sm8350-mtp", "qcom,sm8350"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>; + vdd-l8-supply = <&vreg_s2c_0p8>; + + vreg_s10b_1p8: smps10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1360000>; + }; + + vreg_l1b_0p88: ldo1 { + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_s1c_1p86>; + vdd-l2-l8-supply = <&vreg_s1c_1p86>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s12b_1p25>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_s2c_0p8: smps2 { + regulator-min-microvolt = <640000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l4c_uim1: ldo4 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_uim2: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l10c_1p2: ldo10 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p96: ldo11 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <52 8>; +}; + +&uart2 { + status = "okay"; +}; From e53bdfc009770950dd23023a096542beb5f7df97 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 28 Jan 2021 02:42:20 +0300 Subject: [PATCH 069/100] arm64: dts: qcom: sm8250: Add PCIe support Add PCIe support for Qcom SM8250 SoC. This SoC has 3 PCIe Gen 3 instances based on Designware IP, out of which PCIe0 has 1 lane support and the rest have 2 lane support. Signed-off-by: Manivannan Sadhasivam [DB: add ddrss_sf_tbu clock] Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20210127234221.947306-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 293 +++++++++++++++++++++++++++ 1 file changed, 293 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 61191f7f5861..947e1accae3a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1231,6 +1231,299 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_WIFI_CLKREF_EN>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06200 { + reg = <0 0x1c06200 0 0x170>, /* tx */ + <0 0x1c06400 0 0x200>, /* rx */ + <0 0x1c06800 0 0x1f0>, /* pcs */ + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu", + "ddrss_sf_tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: lanes@1c0e200 { + reg = <0 0x1c0e200 0 0x170>, /* tx0 */ + <0 0x1c0e400 0 0x200>, /* rx0 */ + <0 0x1c0ea00 0 0x1f0>, /* pcs */ + <0 0x1c0e600 0 0x170>, /* tx1 */ + <0 0x1c0e800 0 0x200>, /* rx1 */ + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + + pcie2: pci@1c10000 { + compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; + reg = <0 0x01c10000 0 0x3000>, + <0 0x64000000 0 0xf1d>, + <0 0x64000f20 0 0xa8>, + <0 0x64001000 0 0x1000>, + <0 0x64100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <2>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, + <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_MDM_CLKREF_EN>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu", + "ddrss_sf_tbu"; + + assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1d00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, + <0x100 &apps_smmu 0x1d01 0x1>; + + resets = <&gcc GCC_PCIE_2_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_2_GDSC>; + + phys = <&pcie2_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie2_phy: phy@1c16000 { + compatible = "qcom,sm8250-qmp-modem-pcie-phy"; + reg = <0 0x1c16000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MDM_CLKREF_EN>, + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie2_lane: lanes@1c0e200 { + reg = <0 0x1c16200 0 0x170>, /* tx0 */ + <0 0x1c16400 0 0x200>, /* rx0 */ + <0 0x1c16a00 0 0x1f0>, /* pcs */ + <0 0x1c16600 0 0x170>, /* tx1 */ + <0 0x1c16800 0 0x200>, /* rx1 */ + <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_2_pipe_clk"; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; From 418b4ee165fb225ebe76020d1fdd9bd782292263 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 28 Jan 2021 02:42:21 +0300 Subject: [PATCH 070/100] arm64: dts: qcom: rb5: Enable PCIe ports and PHY RB5 has 3 PCIe ports exposed to connect PCIe client devices. PCIe0 is connected to QCA6391 chipset and others are available on the HS3 expansion connector. Hence, enable all of them. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210127234221.947306-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 117 +++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 58b94ce362b2..26a4a5a6871e 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -655,6 +655,48 @@ wifi-therm@1 { }; }; +&pcie0 { + status = "okay"; + perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; +}; + +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; +}; + +&pcie1 { + status = "okay"; + perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; +}; + +&pcie1_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; +}; + +&pcie2 { + status = "okay"; + perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; + wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_default_state>; +}; + +&pcie2_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; +}; + &pm8150_gpios { gpio-reserved-ranges = <1 1>, <3 2>, <7 1>; gpio-line-names = @@ -1125,6 +1167,81 @@ lt9611_irq_pin: lt9611-irq { bias-disable; }; + pcie0_default_state: pcie0-default { + clkreq { + pins = "gpio80"; + function = "pci_e0"; + bias-pull-up; + }; + + reset-n { + pins = "gpio79"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n { + pins = "gpio81"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + clkreq { + pins = "gpio83"; + function = "pci_e1"; + bias-pull-up; + }; + + reset-n { + pins = "gpio82"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n { + pins = "gpio84"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_default_state: pcie2-default { + clkreq { + pins = "gpio86"; + function = "pci_e2"; + bias-pull-up; + }; + + reset-n { + pins = "gpio85"; + function = "gpio"; + + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + wake-n { + pins = "gpio87"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; + sdc2_default_state: sdc2-default { clk { pins = "sdc2_clk"; From b3a6b088289ee0586b7f1f4977ade6dae06a009a Mon Sep 17 00:00:00 2001 From: Jonathan Albrieux Date: Mon, 25 Jan 2021 10:44:30 +0100 Subject: [PATCH 071/100] arm64: dts: qcom: Add device tree for BQ Aquaris X5 (Longcheer L8910) BQ Aquaris X5 (Longcheer L8910) is a smartphone using the MSM8916 SoC. Add device tree with initial support for: - SDHCI (internal and external storage) - USB Device Mode - UART - Regulators - WiFi/BT - Volume buttons - Vibrator - Touchkeys backlight This device tree is based on downstream device tree from BQ and from Longcheer L8915 device tree. Co-developed-by: Stephan Gerhold Signed-off-by: Stephan Gerhold Signed-off-by: Jonathan Albrieux Link: https://lore.kernel.org/r/20210125094435.7528-2-jonathan.albrieux@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 230 ++++++++++++++++++ 2 files changed, 231 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ac9a1b61aab1..80ff80a9a66c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts new file mode 100644 index 000000000000..7d5eff922f41 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include +#include +#include + +/ { + model = "BQ Aquaris X5 (Longcheer L8910)"; + compatible = "longcheer,l8910", "qcom,msm8916"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&msmgpio 17 GPIO_ACTIVE_HIGH>; + color = ; + default-state = "off"; + function = LED_FUNCTION_KBD_BACKLIGHT; + + pinctrl-names = "default"; + pinctrl-0 = <&button_backlight_default>; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = ; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + button_backlight_default: button-backlight-default { + pins = "gpio17"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + usb_id_default: usb-id-default { + pins = "gpio110"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; From 012e19f435907e2167688ff03c812e86d4e72365 Mon Sep 17 00:00:00 2001 From: Jonathan Albrieux Date: Mon, 25 Jan 2021 10:44:31 +0100 Subject: [PATCH 072/100] arm64: dts: qcom: msm8916: Add blsp_i2c3 MSM8916 has another I2C QUP controller that can be enabled on GPIO 10 and 11. Add blsp_i2c3 to msm8916.dtsi and disable it by default. Reviewed-by: Konrad Dybcio Reviewed-by: Stephan Gerhold Signed-off-by: Jonathan Albrieux Link: https://lore.kernel.org/r/20210125094435.7528-3-jonathan.albrieux@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 15 +++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index 4dc437f13fa5..7dedb91b9930 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -220,6 +220,22 @@ i2c2_sleep: i2c2-sleep { bias-disable; }; + i2c3_default: i2c3-default { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + + drive-strength = <2>; + bias-disable; + }; + + i2c3_sleep: i2c3-sleep { + pins = "gpio10", "gpio11"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + i2c4_default: i2c4-default { pins = "gpio14", "gpio15"; function = "blsp_i2c4"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 8f9a651d3827..c82ac0521e0c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1529,6 +1529,21 @@ blsp_spi2: spi@78b6000 { status = "disabled"; }; + blsp_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_default>; + pinctrl-1 = <&i2c3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_spi3: spi@78b7000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b7000 0x500>; From dcac40943c0503d7ed3958fc86ff0b581776a48f Mon Sep 17 00:00:00 2001 From: Jonathan Albrieux Date: Mon, 25 Jan 2021 10:44:32 +0100 Subject: [PATCH 073/100] arm64: dts: qcom: msm8916-longcheer-l8910: Add imu/magnetometer BQ Aquaris X5 (Longcheer L8910) has: - BMI160 accelerometer and gyroscope sensor - AK09911 magnetometer sensor Add them to the device tree. This patch depends on patch "arm64: dts: qcom: msm8916: Add blsp_i2c3". Reviewed-by: Stephan Gerhold Signed-off-by: Jonathan Albrieux Link: https://lore.kernel.org/r/20210125094435.7528-4-jonathan.albrieux@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 7d5eff922f41..27845189ac2b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -56,6 +56,35 @@ usb_id: usb-id { }; }; +&blsp_i2c3 { + status = "okay"; + + magnetometer@d { + compatible = "asahi-kasei,ak09911"; + reg = <0x0d>; + + vdd-supply = <&pm8916_l17>; + vid-supply = <&pm8916_l6>; + + reset-gpios = <&msmgpio 111 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&mag_reset_default>; + }; + + imu@68 { + compatible = "bosch,bmi160"; + reg = <0x68>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -220,6 +249,14 @@ gpio_keys_default: gpio-keys-default { bias-pull-up; }; + mag_reset_default: mag-reset-default { + pins = "gpio111"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + usb_id_default: usb-id-default { pins = "gpio110"; function = "gpio"; From 886ddcfe4aa44c20e4d0da49af0b01b0e3048322 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 31 Jan 2021 02:38:32 +0100 Subject: [PATCH 074/100] arm64: dts: qcom: msm8994: Add SMP2P nodes They will be required for bringup of remote processors. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 49 +++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index e694aaad3c99..af1a9f7907b8 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -276,6 +276,55 @@ smem { hwlocks = <&tcsr_mutex 3>; }; + smp2p-lpass { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + qcom,ipc = <&apcs 8 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { #address-cells = <1>; From e093d1a2875c1c1050d190fb5de0712173e340ad Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:33 +0100 Subject: [PATCH 075/100] arm64: dts: qcom: msm8994: Fix remaining BLSP errors/mistakes * Move 35500 clock-frequency to kitakami (turns out it's a Sony specific) * Add missing interfaces * Fix the naming scheme * Fix up pin assignments to make all BLSPs work * Add DMA where previously omitted Signed-off-by: Gustave Monce Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-cityman.dts | 2 +- .../msm8994-sony-xperia-kitakami-karin.dts | 2 +- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 24 ++- arch/arm64/boot/dts/qcom/msm8994.dtsi | 173 ++++++++++++++---- 4 files changed, 154 insertions(+), 47 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts index ed9034b96013..2d989a70e0b5 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts @@ -32,7 +32,7 @@ chosen { }; }; -&blsp_i2c1 { +&blsp1_i2c1 { status = "okay"; rmi4-i2c-dev@4b { diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts index 4dcf42eafb3a..a1d1a075941a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dts @@ -12,7 +12,7 @@ / { compatible = "sony,karin-row", "qcom,msm8994"; }; -&blsp_i2c5 { +&blsp2_i2c5 { /* * TI LP8557 backlight driver @ 2c * AD AD7146 touch controller @ 2f diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 586d866188d7..48de66bf19c4 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -94,7 +94,7 @@ tzapp: memory@c7800000 { }; }; -&blsp_spi0 { +&blsp1_spi1 { status = "okay"; /* FPC fingerprint reader */ @@ -102,26 +102,23 @@ &blsp_spi0 { /* I2C1 is disabled on this board */ -&blsp_i2c2 { +&blsp1_i2c2 { status = "okay"; + clock-frequency = <355000>; /* NXP PN547 NFC */ }; -&blsp_i2c4 { +&blsp1_i2c4 { status = "okay"; + clock-frequency = <355000>; /* Empty but active */ }; -&blsp_i2c5 { - status = "okay"; - - /* sii8620 HDMI/MHL bridge */ -}; - -&blsp_i2c6 { +&blsp1_i2c6 { status = "okay"; + clock-frequency = <355000>; touchscreen: rmi4-i2c-dev@2c { compatible = "syna,rmi4-i2c"; @@ -157,6 +154,13 @@ &blsp1_uart2 { status = "okay"; }; +&blsp2_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + /* sii8620 HDMI/MHL bridge */ +}; + &blsp2_uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index af1a9f7907b8..a6148b00e82c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -507,7 +507,7 @@ blsp1_uart2: serial@f991e000 { status = "disabled"; }; - blsp_i2c1: i2c@f9923000 { + blsp1_i2c1: i2c@f9923000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9923000 0x500>; interrupts = ; @@ -515,6 +515,8 @@ blsp_i2c1: i2c@f9923000 { <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_default>; pinctrl-1 = <&i2c1_sleep>; @@ -523,7 +525,7 @@ blsp_i2c1: i2c@f9923000 { status = "disabled"; }; - blsp_spi0: spi@f9923000 { + blsp1_spi1: spi@f9923000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0xf9923000 0x500>; interrupts = ; @@ -534,21 +536,21 @@ blsp_spi0: spi@f9923000 { dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_spi0_default>; - pinctrl-1 = <&blsp1_spi0_sleep>; + pinctrl-0 = <&blsp1_spi1_default>; + pinctrl-1 = <&blsp1_spi1_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; - blsp_i2c2: i2c@f9924000 { + blsp1_i2c2: i2c@f9924000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; - clock-frequency = <355000>; + clock-frequency = <400000>; dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; @@ -561,14 +563,16 @@ blsp_i2c2: i2c@f9924000 { /* I2C3 doesn't exist */ - blsp_i2c4: i2c@f9926000 { + blsp1_i2c4: i2c@f9926000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9926000 0x500>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; clock-names = "iface", "core"; - clock-frequency = <355000>; + clock-frequency = <400000>; + dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_default>; pinctrl-1 = <&i2c4_sleep>; @@ -577,6 +581,42 @@ blsp_i2c4: i2c@f9926000 { status = "disabled"; }; + blsp1_i2c5: i2c@f9927000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9927000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_i2c6: i2c@f9928000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9928000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_default>; + pinctrl-1 = <&i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_dma: dma-controller@f9944000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9944000 0x19000>; @@ -590,28 +630,6 @@ blsp2_dma: dma-controller@f9944000 { qcom,num-ees = <4>; }; - /* According to downstream kernels, i2c6 - * comes before i2c5 address-wise... - */ - - blsp_i2c6: i2c@f9928000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9928000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <355000>; - dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - blsp2_uart2: serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; @@ -627,7 +645,43 @@ blsp2_uart2: serial@f995e000 { status = "disabled"; }; - blsp_i2c5: i2c@f9967000 { + blsp2_i2c1: i2c@f9963000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9963000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c7_default>; + pinctrl-1 = <&i2c7_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_spi4: spi@f9966000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0xf9966000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + spi-max-frequency = <19200000>; + dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_spi10_default>; + pinctrl-1 = <&blsp2_spi10_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c5: i2c@f9967000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9967000 0x500>; interrupts = ; @@ -638,8 +692,8 @@ blsp_i2c5: i2c@f9967000 { dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; + pinctrl-0 = <&i2c11_default>; + pinctrl-1 = <&i2c11_sleep>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -795,7 +849,56 @@ i2c6_sleep: i2c6-sleep { bias-disable; }; - blsp1_spi0_default: blsp1-spi0-default { + i2c7_default: i2c7-default { + function = "blsp_i2c7"; + pins = "gpio44", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + + i2c7_sleep: i2c7-sleep { + function = "gpio"; + pins = "gpio44", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_spi10_default: blsp2-spi10-default { + default { + function = "blsp_spi10"; + pins = "gpio53", "gpio54", "gpio55"; + drive-strength = <10>; + bias-pull-down; + }; + cs { + function = "gpio"; + pins = "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_spi10_sleep: blsp2-spi10-sleep { + pins = "gpio53", "gpio54", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + + i2c11_default: i2c11-default { + function = "blsp_i2c11"; + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + + i2c11_sleep: i2c11-sleep { + function = "gpio"; + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_spi1_default: blsp1-spi1-default { default { function = "blsp_spi1"; pins = "gpio0", "gpio1", "gpio3"; @@ -810,7 +913,7 @@ cs { }; }; - blsp1_spi0_sleep: blsp1-spi0-sleep { + blsp1_spi1_sleep: blsp1-spi1-sleep { pins = "gpio0", "gpio1", "gpio3"; drive-strength = <2>; bias-disable; From 76d0b35c7f84f70219eca8f920b71f9d85f8899e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 31 Jan 2021 02:38:34 +0100 Subject: [PATCH 076/100] arm64: dts: qcom: msm8994: Sort hwlock properly Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index a6148b00e82c..60e04514af70 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -155,6 +155,12 @@ memory { reg = <0 0 0 0>; }; + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x80>; + #hwlock-cells = <1>; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -1003,12 +1009,6 @@ sdc2_data_off: sdc2-data-off { }; }; - tcsr_mutex: hwlock { - compatible = "qcom,tcsr-mutex"; - syscon = <&tcsr_mutex_regs 0 0x80>; - #hwlock-cells = <1>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = , From 976d321f32dcf569738af2bab79d7041a6fb64b5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 31 Jan 2021 02:38:35 +0100 Subject: [PATCH 077/100] arm64: dts: qcom: msm8992: Make the DT an overlay on top of 8994 This saves a good thousand lines of code, perhaps even more in the long run. Co-developed-by: Gustave Monce Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8992-bullhead-rev-101.dts | 2 +- .../boot/dts/qcom/msm8992-xiaomi-libra.dts | 69 +- arch/arm64/boot/dts/qcom/msm8992.dtsi | 772 +----------------- arch/arm64/boot/dts/qcom/msm8994.dtsi | 6 +- 4 files changed, 51 insertions(+), 798 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts index cacbfdbd69e3..23cdcc9f7c72 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -283,7 +283,7 @@ pmi8994_regulators: pmi8994-regulators { }; }; -&sdhc_1 { +&sdhc1 { status = "okay"; mmc-hs400-1_8v; diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 5dab8ee0c7d3..357d55496e75 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -70,21 +70,6 @@ ramoops@dfc00000 { pmsg-size = <0x20000>; }; - continuous_splash: framebuffer@3401000{ - reg = <0x0 0x3401000 0x0 0x2200000>; - no-map; - }; - - dfps_data_mem: dfps_data_mem@3400000 { - reg = <0x0 0x3400000 0x0 0x1000>; - no-map; - }; - - peripheral_region: peripheral_region@7400000 { - reg = <0x0 0x7400000 0x0 0x1c00000>; - no-map; - }; - modem_region: modem_region@9000000 { reg = <0x0 0x9000000 0x0 0x5a00000>; no-map; @@ -97,43 +82,49 @@ tzapp: modem_region@ea00000 { }; }; -&blsp_i2c2 { +&blsp1_i2c2 { status = "okay"; /* Atmel or Synaptics touchscreen */ }; -&blsp_i2c5 { - status = "okay"; - - /* Silabs si4705 FM transmitter */ -}; - -&blsp_i2c6 { - status = "okay"; - - /* NCI NFC, - * TI USB320 Type-C controller, - * Pericom 30216a USB (de)mux switch - */ -}; - -&blsp_i2c7 { - status = "okay"; - - /* cm36686 proximity and ambient light sensor */ -}; - -&blsp_i2c13 { +&blsp1_i2c5 { status = "okay"; /* ST lsm6db0 gyro/accelerometer */ }; +&blsp1_i2c6 { + status = "okay"; + + /* + * NXP NCI NFC, + * TI USB320 Type-C controller, + * Pericom 30216a USB (de)mux switch + */ +}; + +&blsp2_i2c1 { + status = "okay"; + + /* cm36686 proximity and ambient light sensor */ +}; + +&blsp2_i2c5 { + status = "okay"; + + /* Silabs si4705 FM transmitter */ +}; + &blsp2_uart2 { status = "okay"; }; +&peripheral_region { + reg = <0x0 0x7400000 0x0 0x1c00000>; + no-map; +}; + &rpm_requests { pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; @@ -364,7 +355,7 @@ pmi8994_bby: boost-bypass { }; }; -&sdhc_1 { +&sdhc1 { status = "okay"; mmc-hs400-1_8v; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index b2046497dcaa..58fe58cc7703 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -2,767 +2,29 @@ /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. */ -#include -#include -#include +#include "msm8994.dtsi" -/ { - interrupt-parent = <&intc>; +/* 8992 only features 2 A57 cores. */ +/delete-node/ &CPU6; +/delete-node/ &CPU7; +/delete-node/ &cpu6_map; +/delete-node/ &cpu7_map; - #address-cells = <2>; - #size-cells = <2>; +&rpmcc { + compatible = "qcom,rpmcc-msm8992"; +}; - chosen { }; +&tcsr_mutex { + compatible = "qcom,sfpb-mutex"; +}; - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - L2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - next-level-cache = <&L2_1>; - enable-method = "psci"; - L2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - next-level-cache = <&L2_1>; - enable-method = "psci"; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - }; - }; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - firmware { - scm { - compatible = "qcom,scm-msm8994", "qcom,scm"; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "hvc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - smem_region: smem@6a00000 { - reg = <0x0 0x6a00000 0x0 0x200000>; - no-map; - }; - }; - - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_mutex_regs 0x0 0x100>; - #hwlock-cells = <1>; - }; - - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - hwlocks = <&sfpb_mutex 3>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: mailbox@f900d000 { - compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; - reg = <0xf900d000 0x2000>; - #mbox-cells = <1>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - usb3: usb@f92f8800 { - compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; - reg = <0xf92f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB30_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, - <&gcc GCC_USB30_SLEEP_CLK>, - <&gcc GCC_USB30_MOCK_UTMI_CLK>; - clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; - - assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_MASTER_CLK>; - assigned-clock-rates = <19200000>, <120000000>; - - power-domains = <&gcc USB30_GDSC>; - qcom,select-utmi-as-pipe-clk; - - dwc3@f9200000 { - compatible = "snps,dwc3"; - reg = <0xf9200000 0xcc00>; - interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - maximum-speed = "high-speed"; - dr_mode = "peripheral"; - }; - }; - - sdhc_1: sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on - &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off - &sdc1_rclk_off>; - - regulator-always-on; - bus-width = <8>; - non-removable; - - status = "disabled"; - }; - - sdhc_2: sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names = "core", "iface", "xo"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; - - cd-gpios = <&tlmm 100 0>; - bus-width = <4>; - status = "disabled"; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - status = "disabled"; - }; - - blsp_i2c1: i2c@f9923000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9923000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c2: i2c@f9924000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9924000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - /* Somebody was very creative with their numbering scheme downstream... */ - - blsp_i2c13: i2c@f9927000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9927000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c13_default>; - pinctrl-1 = <&i2c13_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c6: i2c@f9928000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9928000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c6_default>; - pinctrl-1 = <&i2c6_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = ; - clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, - <&gcc GCC_BLSP2_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_default>; - pinctrl-1 = <&blsp2_uart2_sleep>; - status = "disabled"; - }; - - blsp_i2c7: i2c@f9963000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9963000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c7_default>; - pinctrl-1 = <&i2c7_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - blsp_i2c5: i2c@f9967000 { - compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0xf9967000 0x500>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; - clock-frequency = <100000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c5_default>; - pinctrl-1 = <&i2c5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8994"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x2000>; - }; - - rpm_msg_ram: memory@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - spmi_bus: spmi@fc4c0000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - reg-names = "core", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - sfpb_mutex_regs: syscon@fd484000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "syscon"; - reg = <0xfd484000 0x400>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&tlmm 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_uart2_default: blsp1-uart2-default { - function = "blsp_uart2"; - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - - blsp1_uart2_sleep: blsp1-uart2-sleep { - function = "gpio"; - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-pull-down; - }; - - blsp2_uart2_default: blsp2-uart2-default { - function = "blsp_uart8"; - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - drive-strength = <16>; - bias-disable; - }; - - blsp2_uart2_sleep: blsp2-uart2-sleep { - function = "gpio"; - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - drive-strength = <2>; - bias-pull-down; - }; - - sdc1_clk_on: clk-on { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <6>; - }; - - sdc1_clk_off: clk-off { - pins = "sdc1_clk"; - bias-disable; - drive-strength = <2>; - }; - - sdc1_cmd_on: cmd-on { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <6>; - }; - - sdc1_cmd_off: cmd-off { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc1_data_on: data-on { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <6>; - }; - - sdc1_data_off: data-off { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc1_rclk_on: rclk-on { - pins = "sdc1_rclk"; - bias-pull-down; - }; - - sdc1_rclk_off: rclk-off { - pins = "sdc1_rclk"; - bias-pull-down; - }; - - i2c1_default: i2c1-default { - function = "blsp_i2c1"; - pins = "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - - i2c1_sleep: i2c1-sleep { - function = "gpio"; - pins = "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - - i2c2_default: i2c2-default { - function = "blsp_i2c2"; - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - - i2c2_sleep: i2c2-sleep { - function = "gpio"; - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - - i2c5_default: i2c5-default { - /* Don't be fooled! Nobody knows the reason why though... */ - function = "blsp_i2c11"; - pins = "gpio83", "gpio84"; - drive-strength = <2>; - bias-disable; - }; - - i2c5_sleep: i2c5-sleep { - function = "gpio"; - pins = "gpio83", "gpio84"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_default: i2c6-default { - function = "blsp_i2c6"; - pins = "gpio28", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - - i2c6_sleep: i2c6-sleep { - function = "gpio"; - pins = "gpio28", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - - i2c7_default: i2c7-default { - function = "blsp_i2c7"; - pins = "gpio43", "gpio44"; - drive-strength = <2>; - bias-disable; - }; - - i2c7_sleep: i2c7-sleep { - function = "gpio"; - pins = "gpio43", "gpio44"; - drive-strength = <2>; - bias-disable; - }; - - i2c13_default: i2c13-default { - /* Not a typo either. */ - function = "blsp_i2c5"; - pins = "gpio23", "gpio24"; - drive-strength = <2>; - bias-disable; - }; - - i2c13_sleep: i2c13-sleep { - function = "gpio"; - pins = "gpio23", "gpio24"; - drive-strength = <2>; - bias-disable; - }; - - sdc2_clk_on: sdc2-clk-on { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - sdc2_clk_off: sdc2-clk-off { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - sdc2_cmd_on: sdc2-cmd-on { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - sdc2_cmd_off: sdc2-cmd-off { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - sdc2_data_on: sdc2-data-on { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - - sdc2_data_off: sdc2-data-off { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - }; - - smd_rpm: smd { - compatible = "qcom,smd"; - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - qcom,local-pid = <0>; - qcom,remote-pid = <6>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8994"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: rpmcc { - compatible = "qcom,rpmcc-msm8992"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8994-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <1>; - }; - rpmpd_opp_svs_krait: opp2 { - opp-level = <2>; - }; - rpmpd_opp_svs_soc: opp3 { - opp-level = <3>; - }; - rpmpd_opp_nom: opp4 { - opp-level = <4>; - }; - rpmpd_opp_turbo: opp5 { - opp-level = <5>; - }; - rpmpd_opp_super_turbo: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , +&timer { + interrupts = , , , ; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; }; +&tlmm { + compatible = "qcom,msm8992-pinctrl"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 60e04514af70..f49d442d2edf 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -132,11 +132,11 @@ core1 { cpu = <&CPU5>; }; - core2 { + cpu6_map: core2 { cpu = <&CPU6>; }; - core3 { + cpu7_map: core3 { cpu = <&CPU7>; }; }; @@ -1009,7 +1009,7 @@ sdc2_data_off: sdc2-data-off { }; }; - timer { + timer: timer { compatible = "arm,armv8-timer"; interrupts = , , From c6e72bd747b014b3fdfba3bf7a744e94447f8b43 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:36 +0100 Subject: [PATCH 078/100] arm64: dts: qcom: msm8992/4-lumia*: Create a common DTS Lumia 950 and 950XL are both based on the Octagon board, sharing the vast majority of components, configuration etc. Commonize it. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 +- .../msm8992-msft-lumia-octagon-talkman.dts | 15 +++++ .../dts/qcom/msm8992-msft-lumia-talkman.dts | 67 ------------------- .../msm8994-msft-lumia-octagon-cityman.dts | 15 +++++ ...an.dts => msm8994-msft-lumia-octagon.dtsi} | 14 ++-- 5 files changed, 38 insertions(+), 77 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dts delete mode 100644 arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dts rename arch/arm64/boot/dts/qcom/{msm8994-msft-lumia-cityman.dts => msm8994-msft-lumia-octagon.dtsi} (81%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 80ff80a9a66c..549a7a2151d4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,10 +13,10 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-cityman.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-octagon-cityman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dts new file mode 100644 index 000000000000..5322b9ce5839 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Gustave Monce + */ + +/dts-v1/; + +#include "msm8992.dtsi" +#include "msm8994-msft-lumia-octagon.dtsi" + +/ { + model = "Microsoft Lumia 950"; + compatible = "microsoft,talkman", "qcom,msm8992"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts deleted file mode 100644 index c337a86a5c77..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2020, Konrad Dybcio - */ - -/dts-v1/; - -#include "msm8992.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include - -/ { - model = "Microsoft Lumia 950"; - compatible = "microsoft,talkman", "qcom,msm8992"; - - /* Most Lumia 950 users use GRUB to load their kernels, - * hence there is no need for msm-id and friends. - */ - - /* This enables graphical output via bootloader-enabled display. - * acpi=no is required due to WP platforms having ACPI support, but - * only for Windows-based OSes. - */ - chosen { - bootargs = "earlycon=efifb console=efifb acpi=no"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - }; -}; - -&blsp_i2c1 { - status = "okay"; - - rmi4-i2c-dev@4b { - compatible = "syna,rmi4-i2c"; - reg = <0x4b>; - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&tlmm>; - interrupts = <77 IRQ_TYPE_EDGE_FALLING>; - - rmi4-f01@1 { - reg = <0x01>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - syna,clip-x-low = <0>; - syna,clip-x-high = <1440>; - syna,clip-y-low = <0>; - syna,clip-y-high = <2560>; - }; - }; -}; - -&sdhc_1 { - status = "okay"; - - mmc-hs200-1_8v; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dts b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dts new file mode 100644 index 000000000000..d0aaf5750c21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Gustave Monce + */ + +/dts-v1/; + +#include "msm8994.dtsi" +#include "msm8994-msft-lumia-octagon.dtsi" + +/ { + model = "Microsoft Lumia 950 XL"; + compatible = "microsoft,cityman", "qcom,msm8994"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi similarity index 81% rename from arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts rename to arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 2d989a70e0b5..53628dd5a172 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -1,20 +1,18 @@ // SPDX-License-Identifier: BSD-3-Clause /* + * Common Board Device Tree for + * Microsoft Mobile MSM8994 Octagon Platforms + * * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, Gustave Monce */ -/dts-v1/; - -#include "msm8994.dtsi" #include "pm8994.dtsi" #include "pmi8994.dtsi" / { - model = "Microsoft Lumia 950 XL"; - compatible = "microsoft,cityman", "qcom,msm8994"; - /* - * Most Lumia 950XL users use GRUB to load their kernels, + * Most Lumia 950/XL users use GRUB to load their kernels, * hence there is no need for msm-id and friends. */ @@ -55,7 +53,7 @@ rmi4-f12@12 { syna,clip-x-low = <0>; syna,clip-x-high = <1440>; syna,clip-y-low = <0>; - syna,clip-y-high = <2660>; + syna,clip-y-high = <2560>; }; }; }; From 70ad85aa12081d79ec6d4c9deab1dbe48f3b1cb8 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:37 +0100 Subject: [PATCH 079/100] arm64: dts: qcom: msm8994-octagon: Fix up the memory map Windows-based devices have a far different memory map than the standard LA one. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-7-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 53628dd5a172..eced5cf3e33f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -10,6 +10,19 @@ #include "pm8994.dtsi" #include "pmi8994.dtsi" +/* + * Delete all generic (msm8994.dtsi) reserved + * memory mappings which are different in this device. + */ +/delete-node/ &adsp_mem; +/delete-node/ &audio_mem; +/delete-node/ &cont_splash_mem; +/delete-node/ &mba_mem; +/delete-node/ &mpss_mem; +/delete-node/ &peripheral_region; +/delete-node/ &rmtfs_mem; +/delete-node/ &smem_mem; + / { /* * Most Lumia 950/XL users use GRUB to load their kernels, @@ -28,6 +41,159 @@ chosen { #size-cells = <2>; ranges; }; + + reserved-memory { + /* + * This device being a WP platform has a very different + * memory layout than other Android based devices. + * This memory layout is directly copied from the original + * device UEFI firmware, and adapted based on observations + * using JTAG for the Qualcomm Peripheral Image regions. + */ + + uefi_mem: memory@200000 { + reg = <0 0x200000 0 0x100000>; + no-map; + }; + + mppark_mem: memory@300000 { + reg = <0 0x300000 0 0x80000>; + no-map; + }; + + fbpt_mem: memory@380000 { + reg = <0 0x380000 0 0x1000>; + no-map; + }; + + dbg2_mem: memory@381000 { + reg = <0 0x381000 0 0x4000>; + no-map; + }; + + capsule_mem: memory@385000 { + reg = <0 0x385000 0 0x1000>; + no-map; + }; + + tpmctrl_mem: memory@386000 { + reg = <0 0x386000 0 0x3000>; + no-map; + }; + + uefiinfo_mem: memory@389000 { + reg = <0 0x389000 0 0x1000>; + no-map; + }; + + reset_mem: memory@389000 { + reg = <0 0x389000 0 0x1000>; + no-map; + }; + + resuncached_mem: memory@38e000 { + reg = <0 0x38e000 0 0x72000>; + no-map; + }; + + disp_mem: memory@400000 { + reg = <0 0x400000 0 0x800000>; + no-map; + }; + + uefistack_mem: memory@c00000 { + reg = <0 0xc00000 0 0x40000>; + no-map; + }; + + cpuvect_mem: memory@c40000 { + reg = <0 0xc40000 0 0x10000>; + no-map; + }; + + rescached_mem: memory@400000 { + reg = <0 0xc50000 0 0xb0000>; + no-map; + }; + + tzapps_mem: memory@6500000 { + reg = <0 0x6500000 0 0x500000>; + no-map; + }; + + smem_mem: memory@6a00000 { + reg = <0 0x6a00000 0 0x200000>; + no-map; + }; + + hyp_mem: memory@6c00000 { + reg = <0 0x6c00000 0 0x100000>; + no-map; + }; + + tz_mem: memory@6d00000 { + reg = <0 0x6d00000 0 0x160000>; + no-map; + }; + + rfsa_adsp_mem: memory@6e60000 { + reg = <0 0x6e60000 0 0x10000>; + no-map; + }; + + rfsa_mpss_mem: memory@6e70000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x6e70000 0 0x10000>; + no-map; + + qcom,client-id = <1>; + }; + + /* + * Value obtained from the device original ACPI DSDT table + * MPSS_EFS / SBL + */ + mba_mem: memory@6e80000 { + reg = <0 0x6e80000 0 0x180000>; + no-map; + }; + + /* + * Peripheral Image loader region begin! + * The region reserved for pil is 0x7000000-0xef00000 + */ + + mpss_mem: memory@7000000 { + reg = <0 0x7000000 0 0x5a00000>; + no-map; + }; + + adsp_mem: memory@ca00000 { + reg = <0 0xca00000 0 0x1800000>; + no-map; + }; + + venus_mem: memory@e200000 { + reg = <0 0xe200000 0 0x500000>; + no-map; + }; + + pil_metadata_mem: memory@e700000 { + reg = <0 0xe700000 0 0x4000>; + no-map; + }; + + memory@e704000 { + reg = <0 0xe704000 0 0x7fc000>; + no-map; + }; + /* Peripheral Image loader region end */ + + cnss_mem: memory@ef00000 { + reg = <0 0xef00000 0 0x300000>; + no-map; + }; + }; }; &blsp1_i2c1 { From 3c0fd4eba208146504e63a8d6eed476fe26c0f40 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:38 +0100 Subject: [PATCH 080/100] arm64: dts: qcom: msm8994-octagon: Add gpio-keys and Hall sensor This enables tje hardware keys as well as the Hall sensor. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-8-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index eced5cf3e33f..840bc38a350c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -9,6 +9,9 @@ #include "pm8994.dtsi" #include "pmi8994.dtsi" +#include +#include +#include /* * Delete all generic (msm8994.dtsi) reserved @@ -42,6 +45,64 @@ chosen { ranges; }; + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + autorepeat; + + volupkey { + label = "Volume Up"; + gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + camsnapkey { + label = "Camera Snapshot"; + gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + camfocuskey { + label = "Camera Focus"; + gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&hall_front_default &hall_back_default>; + + label = "GPIO Hall Effect Sensor"; + + hall-front-sensor { + label = "Hall Effect Front Sensor"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + + hall-back-sensor { + label = "Hall Effect Back Sensor"; + gpios = <&tlmm 75 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + }; + reserved-memory { /* * This device being a WP platform has a very different @@ -235,3 +296,19 @@ &blsp2_uart2 { &sdhc1 { status = "okay"; }; + +&tlmm { + hall_front_default: hall-front-default { + pins = "gpio42"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + hall_back_default: hall-back-default { + pins = "gpio75"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; From 60b214effb80e7592ece7e5fd4370276645bd3a2 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:39 +0100 Subject: [PATCH 081/100] arm64: dts: qcom: msm8994-octagon: Configure regulators Configure the regulators to ensure proper voltages across the board. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-9-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 314 ++++++++++++++++++ 1 file changed, 314 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 840bc38a350c..f89dfc63551a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -293,6 +293,320 @@ &blsp2_uart2 { status = "okay"; }; +&pmi8994_spmi_regulators { + vdd_gfx: s2@1700 { + reg = <0x1700 0x100>; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + }; +}; + +&rpm_requests { + /* These values were taken from the original firmware ACPI tables */ + pm8994_regulators: pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_l1-supply = <&vreg_s1b_1p0>; + vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; + vdd_l3_l11-supply = <&vreg_s3a_1p3>; + vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; + vdd_l5_l7-supply = <&vreg_s5a_2p15>; + vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; + vdd_l8_l16_l30-supply = <&vph_pwr>; + vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; + vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; + vdd_l14_l15-supply = <&vreg_s5a_2p15>; + vdd_l17_l29-supply = <&vph_pwr_bbyp>; + vdd_l20_l21-supply = <&vph_pwr_bbyp>; + vdd_l25-supply = <&vreg_s5a_2p15>; + vdd_lvs1_2-supply = <&vreg_s4a_1p8>; + + /* S1, S2, S6 and S12 are managed by RPMPD */ + + vreg_s3a_1p3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-allow-set-load; + regulator-system-load = <300000>; + }; + + vreg_s4a_1p8: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-always-on; + regulator-system-load = <325000>; + }; + + vreg_s5a_2p15: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-allow-set-load; + regulator-system-load = <325000>; + }; + + vreg_s7a_1p0: s7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + /* + * S8 - SPMI-managed VDD_APC0 + * S9, S10 and S11 (the main one) - SPMI-managed VDD_APC1 + */ + + vreg_l1a_1p0: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l2a_1p25: l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-allow-set-load; + regulator-system-load = <4160>; + }; + + vreg_l3a_1p2: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <80000>; + }; + + vreg_l4a_1p225: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + /* L5 is inaccessible from RPM */ + + vreg_l6a_1p8: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-system-load = <1000>; + }; + + /* L7 is inaccessible from RPM */ + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l11a_1p2: l11 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <35000>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <50000>; + }; + + vreg_l13a_2p95: l13 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <22000>; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <52000>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + vreg_l17a_2p7: l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <300000>; + }; + + vreg_l18a_2p85: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <600000>; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <500000>; + }; + + vreg_l20a_2p95: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-system-load = <570000>; + }; + + vreg_l21a_2p95: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l22a_3p0: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <150000>; + }; + + vreg_l23a_2p8: l23 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <80000>; + }; + + vreg_l24a_3p075: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3150000>; + regulator-allow-set-load; + regulator-system-load = <5800>; + }; + + vreg_l25a_1p1: l25 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <80000>; + }; + + vreg_l26a_1p0: l26 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l27a_1p05: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <500000>; + }; + + vreg_l28a_1p0: l28 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <26000>; + }; + + vreg_l29a_2p8: l29 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <80000>; + }; + + vreg_l30a_1p8: l30 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <2500>; + }; + + vreg_l31a_1p2: l31 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-allow-set-load; + regulator-system-load = <600000>; + }; + + vreg_l32a_1p8: l32 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs1a_1p8: lvs1 { }; + + vreg_lvs2a_1p8: lvs2 { }; + }; + + pmi8994_regulators: pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + vreg_s1b_1p0: s1 { + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + + /* S2 & S3 - VDD_GFX */ + + vph_pwr_bbyp: boost-bypass { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; +}; + &sdhc1 { status = "okay"; }; From 2eae095fc28c5348de39c421447c84bea8a95367 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:40 +0100 Subject: [PATCH 082/100] arm64: dts: qcom: msm8994-octagon: Add QCA6174 bluetooth Configure and enable QCA6174 Bluetooth and required pins. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-10-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index f89dfc63551a..1fa152a3d3cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -45,6 +45,21 @@ chosen { ranges; }; + clocks { + compatible = "simple-bus"; + + divclk4: divclk4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <32768>; + clock-output-names = "divclk4"; + + pinctrl-names = "default"; + pinctrl-0 = <&divclk4_pin_a>; + }; + }; + gpio-keys { compatible = "gpio-keys"; input-name = "gpio-keys"; @@ -291,6 +306,35 @@ &blsp1_uart2 { &blsp2_uart2 { status = "okay"; + + qca6174_bt: bluetooth { + compatible = "qcom,qca6174-bt"; + + enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; + clocks = <&divclk4>; + }; +}; + +&pm8994_gpios { + bt_en_gpios: bt_en_gpios { + pinconf { + pins = "gpio19"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = ; + qcom,drive-strength = ; + bias-pull-down; + }; + }; + + divclk4_pin_a: divclk4 { + pinconf { + pins = "gpio18"; + function = PMIC_GPIO_FUNC_FUNC2; + power-source = ; + bias-disable; + }; + }; }; &pmi8994_spmi_regulators { From 600f91111282dae562b93012c0609d38f8b015be Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:41 +0100 Subject: [PATCH 083/100] arm64: dts: qcom: msm8994-octagon: Configure HD3SS460 Type-C mux pins The driver is not available yet, so hardcode the pins. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-11-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 1fa152a3d3cb..0b8b9e32322a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -337,6 +337,37 @@ pinconf { }; }; +&pmi8994_gpios { + pinctrl-0 = <&hd3ss460_pol &hd3ss460_amsel &hd3ss460_en>; + pinctrl-names = "default"; + + /* + * This device uses a TI HD3SS460 Type-C MUX + * As this device has no driver currently, + * the configuration for USB Face Up is set-up here. + * + * TODO: remove once a driver is available + * TODO: add VBUS GPIO 5 + */ + hd3ss460_pol: pol_low { + pins = "gpio8"; + drive-strength = <3>; + bias-pull-down; + }; + + hd3ss460_amsel: amsel_high { + pins = "gpio9"; + drive-strength = <1>; + bias-pull-up; + }; + + hd3ss460_en: en_high { + pins = "gpio10"; + drive-strength = <1>; + bias-pull-up; + }; +}; + &pmi8994_spmi_regulators { vdd_gfx: s2@1700 { reg = <0x1700 0x100>; From 09179fb6aff47bf61db621dde06b51361a8a8f6b Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:42 +0100 Subject: [PATCH 084/100] arm64: dts: qcom: msm8994-octagon: Add uSD card and disable HS400 on eMMC Lumia 950/XL, like other phones, ship with different storage chips. Some of them are not capable of stable operation at HS400. Disable it. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-12-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 0b8b9e32322a..730bd473be6b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -684,6 +684,27 @@ vph_pwr_bbyp: boost-bypass { &sdhc1 { status = "okay"; + + /* + * This device is shipped with HS400 capabable eMMCs + * However various brands have been used in various product batches, + * including a Samsung eMMC (BGND3R) which features a quirk with HS400. + * Set the speed to HS200 as a safety measure. + */ + mmc-hs200-1_8v; +}; + +&sdhc2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + cd-gpios = <&pm8994_gpios 8 GPIO_ACTIVE_LOW>; }; &tlmm { From 8b65237e4e1b1c44f7be30bfcc4b61a6ee7f3198 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:43 +0100 Subject: [PATCH 085/100] arm64: dts: qcom: msm8994-octagon: Configure Lattice iCE40 FPGA Octagon devices have a Lattice iCE40 FPGA connected over SPI. Configure it. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-13-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 730bd473be6b..0417c31316d3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -304,6 +304,27 @@ &blsp1_uart2 { status = "okay"; }; +&blsp2_spi4 { + status = "okay"; + + /* + * This device is a Lattice UC120 USB-C PD PHY. + * It is actually a Lattice iCE40 FPGA pre-programmed by + * the device firmware with a specific bitstream + * enabling USB Type C PHY functionality. + * Communication is done via a proprietary protocol over SPI. + * + * TODO: Once a proper driver is available, replace this. + */ + uc120: ice5lp2k@0 { + compatible = "lattice,ice40-fpga-mgr"; + reg = <0>; + spi-max-frequency = <5000000>; + cdone-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pmi8994_gpios 4 GPIO_ACTIVE_LOW>; + }; +}; + &blsp2_uart2 { status = "okay"; From da3a82e35e4b24c0392c4667cd7ee1332c0a15e0 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:44 +0100 Subject: [PATCH 086/100] arm64: dts: qcom: msm8994-octagon: Configure PON keys Both the power key and the vol- key are connected over PON. Configure them. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-14-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/pm8994.dtsi | 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 0417c31316d3..1210b470f00c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -358,6 +358,22 @@ pinconf { }; }; +&pm8994_pon { + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0 8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + linux,code = ; + }; + + volwnkey { + compatible = "qcom,pm8941-resin"; + interrupts = <0 8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + linux,code = ; + }; +}; + &pmi8994_gpios { pinctrl-0 = <&hd3ss460_pol &hd3ss460_amsel &hd3ss460_en>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 91fff1f209e0..c3876c82c874 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -43,7 +43,7 @@ rtc@6000 { interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pon@800 { + pm8994_pon: pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x800>; From 7f59caec7b41963efc720dad8e03ba90d930bf86 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 31 Jan 2021 02:38:45 +0100 Subject: [PATCH 087/100] arm64: dts: qcom: msm8994-octagon: Add FM Radio and DDR regulator nodes FAN53526 and SI470X are both connected over blsp2_i2c5. Configure them. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-15-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 1210b470f00c..b1a09d97b485 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -304,6 +304,32 @@ &blsp1_uart2 { status = "okay"; }; +&blsp2_i2c5 { + status = "okay"; + + fm_radio: si4705@11 { + compatible = "silabs,si470x"; + reg = <0x11>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 93 GPIO_ACTIVE_HIGH>; + }; + + vreg_lpddr_1p1: fan53526a@6c { + compatible = "fcs,fan53526"; + reg = <0x6c>; + + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vph_pwr>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; /* Turning off DDR power doesn't sound good. */ + }; + + /* ANX7816 HDMI bridge (needs MDSS HDMI) */ +}; + &blsp2_spi4 { status = "okay"; From 34109bbeccd45f350b70149dcedc1bfbf226ea41 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:46 +0100 Subject: [PATCH 088/100] arm64: dts: qcom: msm8994-octagon: Add NXP NFC node Octagon devices use PN544 connected over I2C. Configure it. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-16-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index b1a09d97b485..86ac180f4893 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -300,6 +300,22 @@ rmi4-f12@12 { }; }; +&blsp1_i2c6 { + status = "okay"; + + pn547: pn547@28 { + compatible = "nxp,pn544-i2c"; + + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; + }; +}; + &blsp1_uart2 { status = "okay"; }; From 3aca45f776e1a908c62a7f52877f94d11197337b Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:47 +0100 Subject: [PATCH 089/100] arm64: dts: qcom: msm8994-octagon: Add sensors on blsp1_i2c5 Add AK09912 magnetometer, ZPA2326 barometer and MPU6500 accelerometer nodes. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-17-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 86ac180f4893..6b692086e7cf 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -300,6 +300,42 @@ rmi4-f12@12 { }; }; +&blsp1_i2c5 { + status = "okay"; + + ak09912: magnetometer@c { + compatible = "asahi-kasei,ak09912"; + reg = <0xc>; + + interrupt-parent = <&tlmm>; + interrupts = <26 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&vreg_l18a_2p85>; + vid-supply = <&vreg_lvs2a_1p8>; + }; + + zpa2326: barometer@5c { + compatible = "murata,zpa2326"; + reg = <0x5c>; + + interrupt-parent = <&tlmm>; + interrupts = <74 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&vreg_lvs2a_1p8>; + }; + + mpu6050: accelerometer@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + + interrupt-parent = <&tlmm>; + interrupts = <64 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&vreg_lvs2a_1p8>; + vddio-supply = <&vreg_lvs2a_1p8>; + }; +}; + &blsp1_i2c6 { status = "okay"; From caea1f74479dcfa09b4f39d95edc580e67058677 Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:48 +0100 Subject: [PATCH 090/100] arm64: dts: qcom: msm8994-octagon: Add TAS2553 codec Lumia 950/XL feature a TAS2553 codec. Configure it using the TAS2552 driver. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-18-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 6b692086e7cf..76619dee71c7 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -300,6 +300,26 @@ rmi4-f12@12 { }; }; +&blsp1_i2c2 { + status = "okay"; + + /* + * This device uses the Texas Instruments TAS2553, however the TAS2552 driver + * seems to work here. In the future a proper driver might need to + * be written for this device. + */ + tas2553: tas2553@40 { + compatible = "ti,tas2552"; + reg = <0x40>; + + vbat-supply = <&vph_pwr>; + iovdd-supply = <&vreg_s4a_1p8>; + avdd-supply = <&vreg_s4a_1p8>; + + enable-gpio = <&pm8994_gpios 12 GPIO_ACTIVE_HIGH>; + }; +}; + &blsp1_i2c5 { status = "okay"; From c636eeb751f695ac0481626e6bd0c1c0188740dd Mon Sep 17 00:00:00 2001 From: Gustave Monce Date: Sun, 31 Jan 2021 02:38:49 +0100 Subject: [PATCH 091/100] arm64: dts: qcom: msm8994-octagon: Add AD7147 and APDS9930 sensors Add and configure AD7147 grip sensor and APDS9930 proximity sensor. Signed-off-by: Gustave Monce Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013853.55810-19-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 76619dee71c7..3a3790a52a2c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -376,6 +376,42 @@ &blsp1_uart2 { status = "okay"; }; +&blsp2_i2c1 { + status = "okay"; + + sideinteraction: ad7147_captouch@2c { + compatible = "ad,ad7147_captouch"; + reg = <0x2c>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&grip_default>; + pinctrl-1 = <&grip_sleep>; + + interrupts = <&tlmm 96 IRQ_TYPE_EDGE_FALLING>; + + button_num = <8>; + touchpad_num = <0>; + wheel_num = <0>; + slider_num = <0>; + + vcc-supply = <&vreg_l18a_2p85>; + }; + + /* + * The QPDS-T900/QPDS-T930 is a customized part built for Nokia + * by Avago. It is very similar to the Avago APDS-9930 with some + * minor differences. In the future a proper driver might need to + * be written for this device. For now this works fine. + */ + qpdst900: qpdst900@39 { + compatible = "avago,apds9930"; + reg = <0x39>; + + interrupt-parent = <&tlmm>; + interrupts = <40 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &blsp2_i2c5 { status = "okay"; @@ -843,6 +879,20 @@ &sdhc2 { }; &tlmm { + grip_default: grip-default { + pins = "gpio39"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + grip_sleep: grip-sleep { + pins = "gpio39"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + hall_front_default: hall-front-default { pins = "gpio42"; function = "gpio"; From d5ae2528b0b56cf054b27d48b0cb85330900082f Mon Sep 17 00:00:00 2001 From: Vincent Knecht Date: Sat, 23 Jan 2021 11:44:16 +0100 Subject: [PATCH 092/100] arm64: dts: msm8916: Fix reserved and rfsa nodes unit address Fix `reserved` and `rfsa` unit address according to their reg address Fixes: 7258e10e6a0b ("ARM: dts: msm8916: Update reserved-memory") Signed-off-by: Vincent Knecht Link: https://lore.kernel.org/r/20210123104417.518105-1-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c82ac0521e0c..5353da521974 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -56,7 +56,7 @@ tz@86500000 { no-map; }; - reserved@8668000 { + reserved@86680000 { reg = <0x0 0x86680000 0x0 0x80000>; no-map; }; @@ -69,7 +69,7 @@ rmtfs@86700000 { qcom,client-id = <1>; }; - rfsa@867e00000 { + rfsa@867e0000 { reg = <0x0 0x867e0000 0x0 0x20000>; no-map; }; From 03e6cb3d8af79ff9a4a1b9fecf3866887bfa6465 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 9 Jan 2021 17:29:55 +0100 Subject: [PATCH 093/100] arm64: dts: qcom: msm8998: Merge in msm8998-pins.dtsi to msm8998.dtsi This is the usual way of handling pin configuration upstream now, so align to it. Signed-off-by: Konrad Dybcio Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20210109163001.146867-2-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998-pins.dtsi | 108 --------------------- arch/arm64/boot/dts/qcom/msm8998.dtsi | 106 +++++++++++++++++++- 2 files changed, 104 insertions(+), 110 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/msm8998-pins.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi deleted file mode 100644 index 7c222cbf19d9..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ - -&tlmm { - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 mA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 mA */ - }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 mA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio95"; - function = "gpio"; - }; - - config { - pins = "gpio95"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 mA */ - }; - }; - - blsp1_uart3_on: blsp1_uart3_on { - tx { - pins = "gpio45"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio46"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - cts { - pins = "gpio47"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - - rfr { - pins = "gpio48"; - function = "blsp_uart3_a"; - drive-strength = <2>; - bias-disable; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index ebdaaf1dfca4..699bd67efcd0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1073,6 +1073,110 @@ tlmm: pinctrl@3400000 { #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_cd_on: sdc2_cd_on { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_cd_off: sdc2_cd_off { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + blsp1_uart3_on: blsp1_uart3_on { + tx { + pins = "gpio45"; + function = "blsp_uart3_a"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio46"; + function = "blsp_uart3_a"; + drive-strength = <2>; + bias-disable; + }; + + cts { + pins = "gpio47"; + function = "blsp_uart3_a"; + drive-strength = <2>; + bias-disable; + }; + + rfr { + pins = "gpio48"; + function = "blsp_uart3_a"; + drive-strength = <2>; + bias-disable; + }; + }; }; remoteproc_mss: remoteproc@4080000 { @@ -2110,5 +2214,3 @@ wifi: wifi@18800000 { }; }; }; - -#include "msm8998-pins.dtsi" From 6845359eea47afed5fa81571a526418228b93580 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 9 Jan 2021 17:29:56 +0100 Subject: [PATCH 094/100] arm64: dts: qcom: msm8998: Add DMA to I2C hosts Add DMA properties to I2C hosts to allow for DMA transfers. Signed-off-by: Konrad Dybcio Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20210109163001.146867-3-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 699bd67efcd0..eadac13ff975 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1893,6 +1893,8 @@ blsp1_i2c1: i2c@c175000 { clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -1908,6 +1910,8 @@ blsp1_i2c2: i2c@c176000 { clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -1923,6 +1927,8 @@ blsp1_i2c3: i2c@c177000 { clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -1938,6 +1944,8 @@ blsp1_i2c4: i2c@c178000 { clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -1953,6 +1961,8 @@ blsp1_i2c5: i2c@c179000 { clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -1968,6 +1978,8 @@ blsp1_i2c6: i2c@c17a000 { clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -1975,6 +1987,19 @@ blsp1_i2c6: i2c@c17a000 { #size-cells = <0>; }; + blsp2_dma: dma@c184000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0c184000 0x25000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <18>; + qcom,num-ees = <4>; + }; + blsp2_uart1: serial@c1b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x0c1b0000 0x1000>; @@ -1993,6 +2018,8 @@ blsp2_i2c0: i2c@c1b5000 { clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -2008,6 +2035,8 @@ blsp2_i2c1: i2c@c1b6000 { clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -2023,6 +2052,8 @@ blsp2_i2c2: i2c@c1b7000 { clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -2038,6 +2069,8 @@ blsp2_i2c3: i2c@c1b8000 { clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -2053,6 +2086,8 @@ blsp2_i2c4: i2c@c1b9000 { clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; @@ -2068,6 +2103,8 @@ blsp2_i2c5: i2c@c1ba000 { clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; + dma-names = "tx", "rx"; clock-frequency = <400000>; status = "disabled"; From 0fee55fc0de71bcb68e1c2cc1c171c3576da7568 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 9 Jan 2021 17:29:57 +0100 Subject: [PATCH 095/100] arm64: dts: qcom: msm8998: Add I2C pinctrl and fix BLSP2_I2C naming The BLSP2-connected interfaces started from 0 which is.. misleading to say the least.. the clock names corresponding to these started from 1, so let's align to that so as to reduce confusion. Signed-off-by: Konrad Dybcio Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20210109163001.146867-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 216 +++++++++++++++++++++++++- 1 file changed, 210 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index eadac13ff975..c7d6dbd24f1e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1177,6 +1177,174 @@ rfr { bias-disable; }; }; + + blsp1_i2c1_default: blsp1-i2c1-default { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c1_sleep: blsp1-i2c1-sleep { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c2_default: blsp1-i2c2-default { + pins = "gpio32", "gpio33"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c2_sleep: blsp1-i2c2-sleep { + pins = "gpio32", "gpio33"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c3_default: blsp1-i2c3-default { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c3_sleep: blsp1-i2c3-sleep { + pins = "gpio47", "gpio48"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c4_default: blsp1-i2c4-default { + pins = "gpio10", "gpio11"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c4_sleep: blsp1-i2c4-sleep { + pins = "gpio10", "gpio11"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c5_default: blsp1-i2c5-default { + pins = "gpio87", "gpio88"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c5_sleep: blsp1-i2c5-sleep { + pins = "gpio87", "gpio88"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp1_i2c6_default: blsp1-i2c6-default { + pins = "gpio43", "gpio44"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + blsp1_i2c6_sleep: blsp1-i2c6-sleep { + pins = "gpio43", "gpio44"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-pull-up; + }; + /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ + blsp2_i2c1_default: blsp2-i2c1-default { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c1_sleep: blsp2-i2c1-sleep { + pins = "gpio55", "gpio56"; + function = "blsp_i2c7"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp2_i2c2_default: blsp2-i2c2-default { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c2_sleep: blsp2-i2c2-sleep { + pins = "gpio6", "gpio7"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp2_i2c3_default: blsp2-i2c3-default { + pins = "gpio51", "gpio52"; + function = "blsp_i2c9"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c3_sleep: blsp2-i2c3-sleep { + pins = "gpio51", "gpio52"; + function = "blsp_i2c9"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp2_i2c4_default: blsp2-i2c4-default { + pins = "gpio67", "gpio68"; + function = "blsp_i2c10"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c4_sleep: blsp2-i2c4-sleep { + pins = "gpio67", "gpio68"; + function = "blsp_i2c10"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp2_i2c5_default: blsp2-i2c5-default { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c5_sleep: blsp2-i2c5-sleep { + pins = "gpio60", "gpio61"; + function = "blsp_i2c11"; + drive-strength = <2>; + bias-pull-up; + }; + + blsp2_i2c6_default: blsp2-i2c6-default { + pins = "gpio83", "gpio84"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_i2c6_sleep: blsp2-i2c6-sleep { + pins = "gpio83", "gpio84"; + function = "blsp_i2c12"; + drive-strength = <2>; + bias-pull-up; + }; }; remoteproc_mss: remoteproc@4080000 { @@ -1895,6 +2063,9 @@ blsp1_i2c1: i2c@c175000 { clock-names = "core", "iface"; dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c1_default>; + pinctrl-1 = <&blsp1_i2c1_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -1912,6 +2083,9 @@ blsp1_i2c2: i2c@c176000 { clock-names = "core", "iface"; dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -1929,6 +2103,9 @@ blsp1_i2c3: i2c@c177000 { clock-names = "core", "iface"; dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c3_default>; + pinctrl-1 = <&blsp1_i2c3_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -1946,6 +2123,9 @@ blsp1_i2c4: i2c@c178000 { clock-names = "core", "iface"; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c4_default>; + pinctrl-1 = <&blsp1_i2c4_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -1963,6 +2143,9 @@ blsp1_i2c5: i2c@c179000 { clock-names = "core", "iface"; dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c5_default>; + pinctrl-1 = <&blsp1_i2c5_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -1980,6 +2163,9 @@ blsp1_i2c6: i2c@c17a000 { clock-names = "core", "iface"; dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c6_default>; + pinctrl-1 = <&blsp1_i2c6_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -2010,7 +2196,7 @@ blsp2_uart1: serial@c1b0000 { status = "disabled"; }; - blsp2_i2c0: i2c@c1b5000 { + blsp2_i2c1: i2c@c1b5000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x0c1b5000 0x600>; interrupts = ; @@ -2020,6 +2206,9 @@ blsp2_i2c0: i2c@c1b5000 { clock-names = "core", "iface"; dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -2027,7 +2216,7 @@ blsp2_i2c0: i2c@c1b5000 { #size-cells = <0>; }; - blsp2_i2c1: i2c@c1b6000 { + blsp2_i2c2: i2c@c1b6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x0c1b6000 0x600>; interrupts = ; @@ -2037,6 +2226,9 @@ blsp2_i2c1: i2c@c1b6000 { clock-names = "core", "iface"; dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c2_default>; + pinctrl-1 = <&blsp2_i2c2_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -2044,7 +2236,7 @@ blsp2_i2c1: i2c@c1b6000 { #size-cells = <0>; }; - blsp2_i2c2: i2c@c1b7000 { + blsp2_i2c3: i2c@c1b7000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x0c1b7000 0x600>; interrupts = ; @@ -2054,6 +2246,9 @@ blsp2_i2c2: i2c@c1b7000 { clock-names = "core", "iface"; dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c3_default>; + pinctrl-1 = <&blsp2_i2c3_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -2061,7 +2256,7 @@ blsp2_i2c2: i2c@c1b7000 { #size-cells = <0>; }; - blsp2_i2c3: i2c@c1b8000 { + blsp2_i2c4: i2c@c1b8000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x0c1b8000 0x600>; interrupts = ; @@ -2071,6 +2266,9 @@ blsp2_i2c3: i2c@c1b8000 { clock-names = "core", "iface"; dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c4_default>; + pinctrl-1 = <&blsp2_i2c4_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -2078,7 +2276,7 @@ blsp2_i2c3: i2c@c1b8000 { #size-cells = <0>; }; - blsp2_i2c4: i2c@c1b9000 { + blsp2_i2c5: i2c@c1b9000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x0c1b9000 0x600>; interrupts = ; @@ -2088,6 +2286,9 @@ blsp2_i2c4: i2c@c1b9000 { clock-names = "core", "iface"; dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c5_default>; + pinctrl-1 = <&blsp2_i2c5_sleep>; clock-frequency = <400000>; status = "disabled"; @@ -2095,7 +2296,7 @@ blsp2_i2c4: i2c@c1b9000 { #size-cells = <0>; }; - blsp2_i2c5: i2c@c1ba000 { + blsp2_i2c6: i2c@c1ba000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x0c1ba000 0x600>; interrupts = ; @@ -2105,6 +2306,9 @@ blsp2_i2c5: i2c@c1ba000 { clock-names = "core", "iface"; dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c6_default>; + pinctrl-1 = <&blsp2_i2c6_sleep>; clock-frequency = <400000>; status = "disabled"; From c43cfc549fdb870857d58063b6268f083b132b48 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 9 Jan 2021 17:29:58 +0100 Subject: [PATCH 096/100] arm64: dts: qcom: msm8998: Add capacity-dmips-mhz to CPU cores Add capacity-dmips-mhz to ensure the scheduler can efficiently make use of the big.LITTLE core configuration. Signed-off-by: Konrad Dybcio Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20210109163001.146867-5-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c7d6dbd24f1e..b2481043205a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -133,6 +133,7 @@ CPU0: cpu@0 { compatible = "qcom,kryo280"; reg = <0x0 0x0>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L2_0: l2-cache { @@ -152,6 +153,7 @@ CPU1: cpu@1 { compatible = "qcom,kryo280"; reg = <0x0 0x1>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L1_I_1: l1-icache { @@ -167,6 +169,7 @@ CPU2: cpu@2 { compatible = "qcom,kryo280"; reg = <0x0 0x2>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L1_I_2: l1-icache { @@ -182,6 +185,7 @@ CPU3: cpu@3 { compatible = "qcom,kryo280"; reg = <0x0 0x3>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L1_I_3: l1-icache { @@ -197,6 +201,7 @@ CPU4: cpu@100 { compatible = "qcom,kryo280"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L2_1: l2-cache { @@ -216,6 +221,7 @@ CPU5: cpu@101 { compatible = "qcom,kryo280"; reg = <0x0 0x101>; enable-method = "psci"; + capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L1_I_101: l1-icache { @@ -231,6 +237,7 @@ CPU6: cpu@102 { compatible = "qcom,kryo280"; reg = <0x0 0x102>; enable-method = "psci"; + capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L1_I_102: l1-icache { @@ -246,6 +253,7 @@ CPU7: cpu@103 { compatible = "qcom,kryo280"; reg = <0x0 0x103>; enable-method = "psci"; + capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L1_I_103: l1-icache { From a72848e8a4d761dccddf6af93e8248384986928f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 9 Jan 2021 17:29:59 +0100 Subject: [PATCH 097/100] arm64: dts: qcom: msm8998: Disable some components by default Some components (like PCIe) are not used on all devices and with a certain firmware configuration they might end up triggering a force reboot or a Synchronous Abort. This commit brings no functional difference as the nodes are enabled on devices which didn't disable them previously. Signed-off-by: Konrad Dybcio Tested-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20210109163001.146867-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 +++++- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi index 00d84fb21798..b500f24d47bc 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi @@ -74,6 +74,14 @@ &CPU7 { cpu-idle-states = <&BIG_CPU_SLEEP_1>; }; +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + &pm8005_lsid1 { pm8005-regulators { compatible = "qcom,pm8005-regulators"; @@ -295,6 +303,14 @@ &sdhc2 { pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; }; +&ufshc { + status = "okay"; +}; + +&ufsphy { + status = "okay"; +}; + &usb3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi index cec42437b302..c1ef0c71d5f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi @@ -106,6 +106,14 @@ &funnel5 { // status = "okay"; }; +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + &pm8005_lsid1 { pm8005-regulators { compatible = "qcom,pm8005-regulators"; @@ -345,6 +353,7 @@ &stm { }; &ufshc { + status = "okay"; vcc-supply = <&vreg_l20a_2p95>; vccq-supply = <&vreg_l26a_1p2>; vccq2-supply = <&vreg_s4a_1p8>; @@ -354,6 +363,7 @@ &ufshc { }; &ufsphy { + status = "okay"; vdda-phy-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l2a_1p2>; vddp-ref-clk-supply = <&vreg_l26a_1p2>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index b2481043205a..65c87a8be5a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -945,6 +945,7 @@ pcie0: pci@1c00000 { num-lanes = <1>; phys = <&pciephy>; phy-names = "pciephy"; + status = "disabled"; ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; @@ -970,11 +971,12 @@ pcie0: pci@1c00000 { perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; }; - phy@1c06000 { + pcie_phy: phy@1c06000 { compatible = "qcom,msm8998-qmp-pcie-phy"; reg = <0x01c06000 0x18c>; #address-cells = <1>; #size-cells = <1>; + status = "disabled"; ranges; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, @@ -1007,6 +1009,7 @@ ufshc: ufshc@1da4000 { phy-names = "ufsphy"; lanes-per-direction = <2>; power-domains = <&gcc UFS_GDSC>; + status = "disabled"; #reset-cells = <1>; clock-names = @@ -1046,6 +1049,7 @@ ufsphy: phy@1da7000 { reg = <0x01da7000 0x18c>; #address-cells = <1>; #size-cells = <1>; + status = "disabled"; ranges; clock-names = From 20fd3b37285b02952b1e843281506db4512803bb Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Fri, 8 Jan 2021 23:45:31 +0530 Subject: [PATCH 098/100] arm64: dts: qcom: sc7180: Add support for gpu fuse Add support for gpu fuse to help identify the supported opps. Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/1610129731-4875-2-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 04445cd3cfd9..284e0f7bea84 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -682,6 +682,11 @@ qusb2p_hstx_trim: hstx-trim-primary@25b { reg = <0x25b 0x1>; bits = <1 3>; }; + + gpu_speed_bin: gpu_speed_bin@1d2 { + reg = <0x1d2 0x2>; + bits = <5 8>; + }; }; sdhc_1: sdhci@7c4000 { @@ -2054,52 +2059,69 @@ gpu: gpu@5000000 { #cooling-cells = <2>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-825000000 { + opp-hz = /bits/ 64 <825000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x04>; + }; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-level = ; opp-peak-kBps = <8532000>; + opp-supported-hw = <0x07>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; opp-level = ; opp-peak-kBps = <7216000>; + opp-supported-hw = <0x07>; }; opp-565000000 { opp-hz = /bits/ 64 <565000000>; opp-level = ; opp-peak-kBps = <5412000>; + opp-supported-hw = <0x07>; }; opp-430000000 { opp-hz = /bits/ 64 <430000000>; opp-level = ; opp-peak-kBps = <5412000>; + opp-supported-hw = <0x07>; }; opp-355000000 { opp-hz = /bits/ 64 <355000000>; opp-level = ; opp-peak-kBps = <3072000>; + opp-supported-hw = <0x07>; }; opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-level = ; opp-peak-kBps = <3072000>; + opp-supported-hw = <0x07>; }; opp-180000000 { opp-hz = /bits/ 64 <180000000>; opp-level = ; opp-peak-kBps = <1804000>; + opp-supported-hw = <0x07>; }; }; }; From 564f18f03e91aa770f4ffccf2fee78d61216a4f4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 24 Dec 2020 13:00:25 +0100 Subject: [PATCH 099/100] arm64: dts: qcom: msm8996: Add missing device_type under pcie[01] Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201224120025.6282-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 7eef07e73e25..ce430ba9c118 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -750,6 +750,8 @@ pcie0: pcie@600000 { ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; + device_type = "pci"; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -802,6 +804,8 @@ pcie1: pcie@608000 { ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; + device_type = "pci"; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; From 7790114893c537176ebab62d002a261b5f01f7a9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Sat, 9 Jan 2021 17:07:59 +0100 Subject: [PATCH 100/100] arm64: dts: qcom: msm8998: Use rpmpd definitions for opp table levels The dt-bindings/power/qcom-rpmpd.h header is being included in this DT but the RPMPD OPP table declarations were using open-coded values: use the definitions found in the aforementioned header. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20210109160759.186990-1-angelogioacchino.delregno@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 65c87a8be5a2..1f2e93aa6553 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -387,43 +387,43 @@ rpmpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmpd_opp_ret: opp1 { - opp-level = <16>; + opp-level = ; }; rpmpd_opp_ret_plus: opp2 { - opp-level = <32>; + opp-level = ; }; rpmpd_opp_min_svs: opp3 { - opp-level = <48>; + opp-level = ; }; rpmpd_opp_low_svs: opp4 { - opp-level = <64>; + opp-level = ; }; rpmpd_opp_svs: opp5 { - opp-level = <128>; + opp-level = ; }; rpmpd_opp_svs_plus: opp6 { - opp-level = <192>; + opp-level = ; }; rpmpd_opp_nom: opp7 { - opp-level = <256>; + opp-level = ; }; rpmpd_opp_nom_plus: opp8 { - opp-level = <320>; + opp-level = ; }; rpmpd_opp_turbo: opp9 { - opp-level = <384>; + opp-level = ; }; rpmpd_opp_turbo_plus: opp10 { - opp-level = <512>; + opp-level = ; }; }; };