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wifi: rtw89: phy: set BB wrap of CIM3K

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The options to enable calibrations of CIM 3rd-order for threshold,
non-bandedge and bandedge.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260511070148.25257-9-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2026-05-11 15:01:45 +08:00
parent ce23c529c7
commit 89ff033872
4 changed files with 40 additions and 4 deletions
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13
drivers/net/wireless/realtek/rtw89/phy.h
View File

@ -589,6 +589,16 @@ enum rtw89_oob_dpd_onoff {
OOB_DPD_ON = 1,
};
enum rtw89_cim3k_onoff {
CIM3K_ON = 1,
CIM3K_OFF = 0,
};
enum rtw89_cim3k_en_dis {
CIM3K_ENABLE = 1,
CIM3K_DISABLE = 0,
};
enum rtw89_rfsi_ctrl_modulation {
RFSI_BPSK = 0,
RFSI_QPSK = 1,
@ -617,6 +627,9 @@ enum rtw89_rfsi_ctrl_modulation {
struct rtw89_bb_wrap_common_data {
struct {
struct rtw89_bb_wrap_data_cim3k {
u8 th, ow, non_bandedge, bandedge;
} cim3k;
u32 rfsi_ct_opt[2];
u8 pb_tb;
} bands[RFSI_CTRL_BAND_NUM];

24
drivers/net/wireless/realtek/rtw89/phy_be.c
View File

@ -964,10 +964,26 @@ static void rtw89_phy_bb_set_mdpd_qam_comp_val(struct rtw89_dev *rtwdev,
static void rtw89_phy_bb_set_cim3k_val(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx mac_idx)
{
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_OW_BE4, 0x0, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_NONBE_BE4, 0x1, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_BANDEDGE_BE4, 0x1, mac_idx);
const struct rtw89_bb_wrap_data *d = rtwdev->phy_info.bb_wrap_data;
const struct rtw89_bb_wrap_data_cim3k *p;
if (!d || !d->common)
return;
p = &d->common->bands[0].cim3k;
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_TH_BE4, p->th, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_OW_BE4, p->ow, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_NONBE_BE4,
p->non_bandedge, mac_idx);
rtw89_write32_idx(rtwdev, R_COMP_CIM3K_BE4, B_COMP_CIM3K_BANDEDGE_BE4,
p->bandedge, mac_idx);
if (rtwdev->chip->chip_id != RTL8922D)
return;
rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_EN, 1, mac_idx);
rtw89_write32_idx(rtwdev, R_CIM3K_SU_FORCE, B_CIM3K_SU_FORCE_VAL, 0, mac_idx);
}
static void rtw89_phy_bb_wrap_tx_rfsi_ctrl_init(struct rtw89_dev *rtwdev,

3
drivers/net/wireless/realtek/rtw89/reg.h
View File

@ -10596,6 +10596,9 @@
#define B_FBTB_CT_MUMIMO_BE4 GENMASK(19, 16)
#define B_FBTB_CT_FTM_BE4 GENMASK(23, 20)
#define B_FBTB_CT_SENS_BE4 GENMASK(27, 24)
#define R_CIM3K_SU_FORCE 0x119F8
#define B_CIM3K_SU_FORCE_EN BIT(17)
#define B_CIM3K_SU_FORCE_VAL BIT(18)
#define R_RFSI_CT_OPT_0_BE4 0x11A94
#define R_RFSI_CT_OPT_8_BE4 0x11A98
#define R_QAM_COMP_TH0_BE4 0x11A9C

4
drivers/net/wireless/realtek/rtw89/rtw8922d.c
View File

@ -289,11 +289,13 @@ static const struct rtw89_efuse_block_cfg rtw8922d_efuse_blocks[] = {
static const struct rtw89_bb_wrap_common_data rtw8922d_bb_wrap_common_data_7025 = {
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_ENABLE, CIM3K_ENABLE},
.rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
_8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
.pb_tb = 3,
},
[RFSI_CTRL_BAND_2GHZ] = {
.cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_ENABLE, CIM3K_ENABLE},
.rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
_8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
.pb_tb = 0,
@ -304,11 +306,13 @@ static const struct rtw89_bb_wrap_common_data rtw8922d_bb_wrap_common_data_7025
static const struct rtw89_bb_wrap_common_data rtw8922d_bb_wrap_common_data_7090 = {
.bands = {
[RFSI_CTRL_BAND_5_6GHZ] = {
.cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_DISABLE, CIM3K_ENABLE},
.rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
_8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
.pb_tb = 3,
},
[RFSI_CTRL_BAND_2GHZ] = {
.cim3k = {CIM3K_OFF, CIM3K_OFF, CIM3K_DISABLE, CIM3K_ENABLE},
.rfsi_ct_opt = {_8nibble(2, 2, 2, 2, 1, 1, 1, 1),
_8nibble(2, 2, 2, 2, 1, 1, 1, 1)},
.pb_tb = 0,