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drm/amdgpu: support gc v9_4_3 ring_test running on all xcc
Each xcc has its own sratch_reg offset Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -227,20 +227,23 @@ static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
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uint32_t tmp = 0;
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unsigned i;
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int r;
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/* scratch_reg0_offset is 32bit even with full XCD config */
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uint32_t scratch_reg0_offset;
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scratch_reg0_offset = SOC15_REG_OFFSET(GC, ring->xcc_id, regSCRATCH_REG0);
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WREG32(scratch_reg0_offset, 0xCAFEDEAD);
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WREG32_SOC15(GC, 0, regSCRATCH_REG0, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(ring, 3);
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if (r)
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return r;
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amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
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amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0) -
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PACKET3_SET_UCONFIG_REG_START);
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amdgpu_ring_write(ring, scratch_reg0_offset - PACKET3_SET_UCONFIG_REG_START);
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amdgpu_ring_write(ring, 0xDEADBEEF);
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amdgpu_ring_commit(ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32_SOC15(GC, 0, regSCRATCH_REG0);
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tmp = RREG32(scratch_reg0_offset);
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if (tmp == 0xDEADBEEF)
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break;
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udelay(1);
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