drm/amdgpu: support gc v9_4_3 ring_test running on all xcc

Each xcc has its own sratch_reg offset

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2022-05-23 13:53:45 +08:00 committed by Alex Deucher
parent ae972ed5e0
commit 89cf4549a9

View File

@ -227,20 +227,23 @@ static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
uint32_t tmp = 0;
unsigned i;
int r;
/* scratch_reg0_offset is 32bit even with full XCD config */
uint32_t scratch_reg0_offset;
scratch_reg0_offset = SOC15_REG_OFFSET(GC, ring->xcc_id, regSCRATCH_REG0);
WREG32(scratch_reg0_offset, 0xCAFEDEAD);
WREG32_SOC15(GC, 0, regSCRATCH_REG0, 0xCAFEDEAD);
r = amdgpu_ring_alloc(ring, 3);
if (r)
return r;
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0) -
PACKET3_SET_UCONFIG_REG_START);
amdgpu_ring_write(ring, scratch_reg0_offset - PACKET3_SET_UCONFIG_REG_START);
amdgpu_ring_write(ring, 0xDEADBEEF);
amdgpu_ring_commit(ring);
for (i = 0; i < adev->usec_timeout; i++) {
tmp = RREG32_SOC15(GC, 0, regSCRATCH_REG0);
tmp = RREG32(scratch_reg0_offset);
if (tmp == 0xDEADBEEF)
break;
udelay(1);