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coresight: Updates for Linux v7.3
This is relatively smaller update for CoreSight/hwtracing subsystem updates. - MAINTAINERS update for HiSilicon PCI Trace & Tune drivers - Minor fixes to hisi_ptt driver - Various fixes to the coresight etm4x dirvers Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuFy0byloRoXZHaWBxcXRZPKyBqEFAmp18fwACgkQxcXRZPKy BqEXARAAln7ZWpWOsmhiNlHPHWSsY0ezUYLrKSsmR80EZkvX6Wk75Ju5r1fH8v/o vG8Dqr8ryIPPDN4JGeXLsymfbctap/3jXFl/Y+ZQeq8BWo6Weriof3/08KR2P1kG bVT8FgcHjY15WzNaTrI10enMfXu8CR9GCqPNI0R72EnKKN0f3kgYin67YE9lS2YO 25Dtl3+PtVD0qN9VxIGPCoh2Njwjre9DCKw+SwlDO97Km+s5uHXI06QJpj7rC27V YEKEFaXiMk8ZrSidXyBE78QOZRjmJ5jNWxOXs8tquw40ootZNLoJ1blx8GOWEukL ppUGYALkzelM6uewxy4W+v66eYQf6xCbIHBRUUa/4zqngJjqmuTbvyDW9bZ1mCCE nd8VuuskMrcM+mxYvBBbiqD/RJyH7eT7IPuXZN0u+wvNV6uiosoRB4VrElwC0NEE gB/DkF1ChBddKCD3xJ1U4oAYRmkEqJ9StzpNz+Jr54Gg62RiWjoxEqhBBULwI3vO gpDgjV9LvVLr2BC2GIk5o2BFE7skJppaP4evKKZSG5uuDc/h7YZvSdl81nYscSG+ kWgFC5MQc0HXBhVw7C+DIJPwsCRN//30wo7wrA8+GiLJ+UffKhsqjH9+jRnEPSkf XKNSpRoP5IeDNWdR5/6I1Kotf0dmF6RYXUOlPs7de2tWFNDIyS8= =iRuU -----END PGP SIGNATURE----- Merge tag 'coresight-next-v7.3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next Suzuki writes: coresight: Updates for Linux v7.3 This is relatively smaller update for CoreSight/hwtracing subsystem updates. - MAINTAINERS update for HiSilicon PCI Trace & Tune drivers - Minor fixes to hisi_ptt driver - Various fixes to the coresight etm4x dirvers Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> * tag 'coresight-next-v7.3' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux: coresight: etm4x: remove redundant fields in etmv4_save_state coresight: etm4x: missing cscfg_csdev_disable_active_config() in perf enable coresight: etm4x: fix leaked trace id coresight: etm4x: fix underflow for usage of (nrseqstate - 1) coresight: etm4x: fix wrong check of etm4x_sspcicrn_present() hwtracing: hisi_ptt: Remove unnecessary trace buffer zeroing in trace_start() hwtracing: hisi_ptt: Propagate DMA reset timeout in trace_start() MAINTAINERS: Update HiSilicon PCI Trace and Tune maintainer coresight: etm3x: Fix cntr_val_show() to match cntr_val_store() behavior
This commit is contained in:
Greg Kroah-Hartman
commit
8992f32c57
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@ -11770,8 +11770,7 @@ F: drivers/perf/hisilicon
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F: tools/perf/pmu-events/arch/arm64/hisilicon/
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HISILICON PTT DRIVER
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M: Yicong Yang <yangyicong@hisilicon.com>
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M: Jonathan Cameron <jonathan.cameron@huawei.com>
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M: Sizhe Liu <liusizhe5@huawei.com>
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L: linux-kernel@vger.kernel.org
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S: Maintained
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F: Documentation/ABI/testing/sysfs-bus-event_source-devices-hisi_ptt
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@ -717,26 +717,19 @@ static DEVICE_ATTR_RW(cntr_rld_event);
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static ssize_t cntr_val_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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int i, ret = 0;
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u32 val;
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struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct etm_config *config = &drvdata->config;
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if (!coresight_get_mode(drvdata->csdev)) {
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spin_lock(&drvdata->spinlock);
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for (i = 0; i < drvdata->nr_cntr; i++)
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ret += sprintf(buf, "counter %d: %x\n",
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i, config->cntr_val[i]);
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val = config->cntr_val[config->cntr_idx];
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spin_unlock(&drvdata->spinlock);
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return ret;
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} else {
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val = etm_readl(drvdata, ETMCNTVRn(config->cntr_idx));
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}
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for (i = 0; i < drvdata->nr_cntr; i++) {
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val = etm_readl(drvdata, ETMCNTVRn(i));
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ret += sprintf(buf, "counter %d: %x\n", i, val);
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}
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return ret;
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return sysfs_emit(buf, "%#x\n", val);
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}
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static ssize_t cntr_val_store(struct device *dev,
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@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
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} else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
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/* sequencer state control registers */
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idx = (offset & GENMASK(3, 0)) / 4;
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if (idx < ETM_MAX_SEQ_STATES) {
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if (idx < ETM_MAX_SEQ_TRANSITIONS) {
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reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx];
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err = 0;
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}
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@ -93,7 +93,7 @@ static int etm4_probe_cpu(unsigned int cpu);
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static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
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{
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return (n < drvdata->nr_ss_cmp) &&
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drvdata->nr_pe &&
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drvdata->nr_pe_cmp &&
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(drvdata->config.ss_status[n] & TRCSSCSRn_PC);
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}
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@ -542,7 +542,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
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etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
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if (drvdata->nr_pe_cmp)
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etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
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for (i = 0; i < drvdata->nrseqstate - 1; i++)
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for (i = 0; i < drvdata->nr_seq_ctrls; i++)
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etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
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if (drvdata->nrseqstate) {
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etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
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@ -756,8 +757,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
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.ATTR_CFG_FLD_timestamp_CFG = U64_MAX,
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};
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struct perf_event_attr *attr = &event->attr;
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unsigned long cfg_hash;
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int preset, cc_threshold;
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int cc_threshold;
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u8 ts_level;
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/* Clear configuration from previous run */
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@ -843,16 +843,6 @@ static int etm4_parse_event_config(struct coresight_device *csdev,
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/* bit[12], Return stack enable bit */
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config->cfg |= TRCCONFIGR_RS;
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/*
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* Set any selected configuration and preset. A zero configid means no
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* configuration active, preset = 0 means no preset selected.
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*/
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cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
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if (cfg_hash) {
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preset = ATTR_CFG_GET_FLD(attr, preset);
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ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
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}
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/* branch broadcast - enable if selected and supported */
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if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) {
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if (!drvdata->trcbb) {
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@ -876,7 +866,9 @@ static int etm4_enable_perf(struct coresight_device *csdev,
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struct coresight_path *path)
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{
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struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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int ret;
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struct perf_event_attr *attr = &event->attr;
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unsigned long cfg_hash;
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int ret, preset;
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if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
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return -EINVAL;
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@ -887,7 +879,19 @@ static int etm4_enable_perf(struct coresight_device *csdev,
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/* Configure the tracer based on the session's specifics */
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ret = etm4_parse_event_config(csdev, event);
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if (ret)
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goto out;
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goto err;
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/*
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* Set any selected configuration and preset. A zero configid means no
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* configuration active, preset = 0 means no preset selected.
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*/
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cfg_hash = ATTR_CFG_GET_FLD(attr, configid);
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if (cfg_hash) {
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preset = ATTR_CFG_GET_FLD(attr, preset);
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ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
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if (ret)
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goto err;
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}
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drvdata->trcid = path->trace_id;
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@ -896,16 +900,19 @@ static int etm4_enable_perf(struct coresight_device *csdev,
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/* And enable it */
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ret = etm4_enable_hw(drvdata);
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out:
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/* Failed to start tracer; roll back to DISABLED mode */
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if (ret) {
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coresight_set_mode(csdev, CS_MODE_DISABLED);
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return ret;
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if (cfg_hash)
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cscfg_csdev_disable_active_config(csdev);
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goto err;
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}
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csdev->path = path;
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return 0;
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err:
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/* Failed to start tracer; roll back to DISABLED mode */
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coresight_set_mode(csdev, CS_MODE_DISABLED);
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return ret;
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}
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static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path)
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@ -919,8 +926,10 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa
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cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
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if (cfg_hash) {
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ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
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if (ret)
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if (ret) {
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etm4_release_trace_id(drvdata);
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return ret;
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}
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}
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raw_spin_lock(&drvdata->spinlock);
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@ -1508,6 +1517,8 @@ static void etm4_init_arch_data(void *info)
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drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
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/* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
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drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
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if (drvdata->nrseqstate)
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drvdata->nr_seq_ctrls = ETM_MAX_SEQ_TRANSITIONS;
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/* NUMCNTR, bits[30:28] number of counters available for tracing */
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drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
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@ -1896,7 +1907,7 @@ static int etm4_cpu_save(struct coresight_device *csdev)
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if (drvdata->nr_pe_cmp)
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state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
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for (i = 0; i < drvdata->nrseqstate - 1; i++)
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for (i = 0; i < drvdata->nr_seq_ctrls; i++)
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state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
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if (drvdata->nrseqstate) {
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@ -2009,7 +2020,7 @@ static void etm4_cpu_restore(struct coresight_device *csdev)
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if (drvdata->nr_pe_cmp)
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etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
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for (i = 0; i < drvdata->nrseqstate - 1; i++)
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for (i = 0; i < drvdata->nr_seq_ctrls; i++)
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etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
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if (drvdata->nrseqstate) {
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|
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@ -223,7 +223,7 @@ static ssize_t reset_store(struct device *dev,
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config->vipcssctlr = 0x0;
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/* Disable seq events */
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for (i = 0; i < drvdata->nrseqstate-1; i++)
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for (i = 0; i < drvdata->nr_seq_ctrls; i++)
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config->seq_ctrl[i] = 0x0;
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config->seq_rst = 0x0;
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config->seq_state = 0x0;
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@ -1395,9 +1395,11 @@ static ssize_t seq_idx_store(struct device *dev,
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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struct etmv4_config *config = &drvdata->config;
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if (!drvdata->nr_seq_ctrls)
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return -ENOTSUPP;
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if (kstrtoul(buf, 16, &val))
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return -EINVAL;
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if (val >= drvdata->nrseqstate - 1)
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if (val >= drvdata->nr_seq_ctrls)
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return -EINVAL;
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/*
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|
|
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@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
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#define ETM_MAX_NR_PE 8
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#define ETMv4_MAX_CNTR 4
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#define ETM_MAX_SEQ_STATES 4
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#define ETM_MAX_SEQ_TRANSITIONS 3
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#define ETM_MAX_EXT_INP_SEL 4
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#define ETM_MAX_EXT_INP 256
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#define ETM_MAX_EXT_OUT 4
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@ -877,7 +878,7 @@ struct etmv4_config {
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u32 vipcssctlr;
|
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u8 seq_idx;
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u8 syncfreq;
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u32 seq_ctrl[ETM_MAX_SEQ_STATES];
|
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u32 seq_ctrl[ETM_MAX_SEQ_TRANSITIONS];
|
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u32 seq_rst;
|
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u32 seq_state;
|
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u8 cntr_idx;
|
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|
|
@ -928,7 +929,7 @@ struct etmv4_save_state {
|
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u32 trcvissctlr;
|
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u32 trcvipcssctlr;
|
||||
|
||||
u32 trcseqevr[ETM_MAX_SEQ_STATES];
|
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u32 trcseqevr[ETM_MAX_SEQ_TRANSITIONS];
|
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u32 trcseqrstevr;
|
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u32 trcseqstr;
|
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u32 trcextinselr;
|
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|
|
@ -953,11 +954,6 @@ struct etmv4_save_state {
|
|||
|
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u32 trcclaimset;
|
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|
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u32 cntr_val[ETMv4_MAX_CNTR];
|
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u32 seq_state;
|
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u32 vinst_ctrl;
|
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u32 ss_status[ETM_MAX_SS_CMP];
|
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|
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u32 trcpdcr;
|
||||
};
|
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|
||||
|
|
@ -981,6 +977,7 @@ struct etmv4_save_state {
|
|||
* @numcidc: Number of contextID comparators.
|
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* @numvmidc: Number of VMID comparators.
|
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* @nrseqstate: The number of sequencer states that are implemented.
|
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* @nr_seq_ctrls: The number of sequence state transition control registers.
|
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* @nr_event: Indicates how many events the trace unit support.
|
||||
* @nr_resource:The number of resource selection pairs available for tracing.
|
||||
* @nr_ss_cmp: Number of single-shot comparator controls that are available.
|
||||
|
|
@ -1046,6 +1043,7 @@ struct etmv4_drvdata {
|
|||
u8 numextinsel;
|
||||
u8 numvmidc;
|
||||
u8 nrseqstate;
|
||||
u8 nr_seq_ctrls;
|
||||
u8 nr_event;
|
||||
u8 nr_resource;
|
||||
u8 nr_ss_cmp;
|
||||
|
|
|
|||
|
|
@ -171,13 +171,13 @@ static bool hisi_ptt_wait_trace_hw_idle(struct hisi_ptt *hisi_ptt)
|
|||
HISI_PTT_WAIT_TRACE_TIMEOUT_US);
|
||||
}
|
||||
|
||||
static void hisi_ptt_wait_dma_reset_done(struct hisi_ptt *hisi_ptt)
|
||||
static bool hisi_ptt_wait_dma_reset_done(struct hisi_ptt *hisi_ptt)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
readl_poll_timeout_atomic(hisi_ptt->iobase + HISI_PTT_TRACE_WR_STS,
|
||||
val, !val, HISI_PTT_RESET_POLL_INTERVAL_US,
|
||||
HISI_PTT_RESET_TIMEOUT_US);
|
||||
return !readl_poll_timeout_atomic(hisi_ptt->iobase + HISI_PTT_TRACE_WR_STS,
|
||||
val, !val, HISI_PTT_RESET_POLL_INTERVAL_US,
|
||||
HISI_PTT_RESET_TIMEOUT_US);
|
||||
}
|
||||
|
||||
static void hisi_ptt_trace_end(struct hisi_ptt *hisi_ptt)
|
||||
|
|
@ -194,7 +194,6 @@ static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt)
|
|||
{
|
||||
struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl;
|
||||
u32 val;
|
||||
int i;
|
||||
|
||||
/* Check device idle before start trace */
|
||||
if (!hisi_ptt_wait_trace_hw_idle(hisi_ptt)) {
|
||||
|
|
@ -202,14 +201,18 @@ static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt)
|
|||
return -EBUSY;
|
||||
}
|
||||
|
||||
ctrl->started = true;
|
||||
|
||||
/* Reset the DMA before start tracing */
|
||||
val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
|
||||
val |= HISI_PTT_TRACE_CTRL_RST;
|
||||
writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
|
||||
|
||||
hisi_ptt_wait_dma_reset_done(hisi_ptt);
|
||||
if (!hisi_ptt_wait_dma_reset_done(hisi_ptt)) {
|
||||
pci_err(hisi_ptt->pdev, "timed out waiting for DMA reset\n");
|
||||
val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
|
||||
val &= ~HISI_PTT_TRACE_CTRL_RST;
|
||||
writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
|
||||
val &= ~HISI_PTT_TRACE_CTRL_RST;
|
||||
|
|
@ -218,10 +221,6 @@ static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt)
|
|||
/* Reset the index of current buffer */
|
||||
hisi_ptt->trace_ctrl.buf_index = 0;
|
||||
|
||||
/* Zero the trace buffers */
|
||||
for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++)
|
||||
memset(ctrl->trace_buf[i].addr, 0, HISI_PTT_TRACE_BUF_SIZE);
|
||||
|
||||
/* Clear the interrupt status */
|
||||
writel(HISI_PTT_TRACE_INT_STAT_MASK, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT);
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writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK);
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||||
|
|
@ -234,6 +233,8 @@ static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt)
|
|||
if (!hisi_ptt->trace_ctrl.is_port)
|
||||
val |= HISI_PTT_TRACE_CTRL_FILTER_MODE;
|
||||
|
||||
ctrl->started = true;
|
||||
|
||||
/* Start the Trace */
|
||||
val |= HISI_PTT_TRACE_CTRL_EN;
|
||||
writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user