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drm/xe/xe2_hpg: Correct implementation of Wa_16025250150

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Wa_16025250150 asks us to set five register fields of the register to
0x1 each.  However we were just OR'ing this into the existing register
value (which has a default of 0x4 for each nibble-sized field) resulting
in final field values of 0x5 instead of the desired 0x1.  Correct the
RTP programming (use FIELD_SET instead of SET) to ensure each field is
assigned to exactly the value we want.

Cc: Aradhya Bhatia <aradhya.bhatia@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: stable@vger.kernel.org # v6.16+
Fixes: 7654d51f1f ("drm/xe/xe2hpg: Add Wa_16025250150")
Reviewed-by: Ngai-Mint Kwan <ngai-mint.kwan@linux.intel.com>
Link: https://patch.msgid.link/20260227164341.3600098-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit d139209ef8)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2026-02-27 08:43:41 -08:00 committed by Rodrigo Vivi
parent b3368ecca9
commit 89865e6dc8
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GPG Key ID: FA625F640EEB13CA
1 changed files with 7 additions and 6 deletions
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13
drivers/gpu/drm/xe/xe_wa.c
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@ -241,12 +241,13 @@ static const struct xe_rtp_entry_sr gt_was[] = {
{ XE_RTP_NAME("16025250150"),
XE_RTP_RULES(GRAPHICS_VERSION(2001)),
XE_RTP_ACTIONS(SET(LSN_VC_REG2,
LSN_LNI_WGT(1) |
LSN_LNE_WGT(1) |
LSN_DIM_X_WGT(1) |
LSN_DIM_Y_WGT(1) |
LSN_DIM_Z_WGT(1)))
XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2,
LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK |
LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK |
LSN_DIM_Z_WGT_MASK,
LSN_LNI_WGT(1) | LSN_LNE_WGT(1) |
LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) |
LSN_DIM_Z_WGT(1)))
},
/* Xe2_HPM */