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perf/amd/ibs: Limit ldlat->l3missonly dependency to Zen5

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The ldlat dependency on l3missonly is specific to Zen 5; newer generations
are not affected. This quirk is documented as an erratum in the following
Revision Guide.

  Erratum: 1606 IBS (Instruction Based Sampling) OP Load Latency Filtering
           May Capture Unwanted Samples When L3Miss Filtering is Disabled

  Revision Guide for AMD Family 1Ah Models 00h-0Fh Processors,
  Pub. 58251 Rev. 1.30 July 2025
  https://bugzilla.kernel.org/attachment.cgi?id=309193

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Namhyung Kim <namhyung@kernel.org>
Link: https://patch.msgid.link/20260216042216.1440-3-ravi.bangoria@amd.com
This commit is contained in:
Ravi Bangoria 2026-02-16 04:22:13 +00:00 committed by Peter Zijlstra
parent 01336b5559
commit 898138efc9
1 changed files with 4 additions and 1 deletions
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5
arch/x86/events/amd/ibs.c
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@ -356,7 +356,10 @@ static int perf_ibs_init(struct perf_event *event)
ldlat >>= 7;
config |= (ldlat - 1) << 59;
config |= IBS_OP_L3MISSONLY | IBS_OP_LDLAT_EN;
config |= IBS_OP_LDLAT_EN;
if (cpu_feature_enabled(X86_FEATURE_ZEN5))
config |= IBS_OP_L3MISSONLY;
}
/*