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KVM: arm64: gic-v5: Cache host IRS ID registers

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KVM needs access to the host IRS configuration frame to configure
virtual-machine resources. The frame ID registers describe the
capabilities available to KVM.

Cache IRS_IDR2, IRS_IDR3, and IRS_IDR4 rather than extracting their
individual fields into kvm_vgic_global_state. Accessor helpers derive
the required capabilities from the cached registers.

Use the cached IRS_IDR4 VPE capacity to limit the maximum number of
vCPUs, while retaining VGIC_V5_MAX_CPUS as KVM's own upper bound.

Keeping the raw register values lets KVM adjust the exposed
capabilities when needed, as is done for ICH_VTR_EL2, and avoids tying
future EL2 code to the layout of kvm_vgic_global_state.

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Link: https://patch.msgid.link/20260904113404.4051341-8-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Sascha Bischoff 2026-09-04 11:37:50 +00:00 committed by Marc Zyngier
parent be0b3fd634
commit 896b6a1025
2 changed files with 95 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/arm64/kvm/vgic/vgic-v5.c
View File

@ -11,6 +11,7 @@
#include "vgic.h"
#define ppi_caps kvm_vgic_global_state.vgic_v5_ppi_caps
#define irs_caps kvm_vgic_global_state.vgic_v5_irs_caps
/*
* Not all PPIs are guaranteed to be implemented for GICv5. Deterermine which
@ -34,6 +35,21 @@ static void vgic_v5_get_implemented_ppis(void)
__assign_bit(GICV5_ARCH_PPI_PMUIRQ, ppi_caps.impl_ppi_mask, system_supports_pmuv3());
}
static u32 irs_readl_relaxed(const u32 reg_offset)
{
return readl_relaxed(irs_caps.irs_base + reg_offset);
}
static void vgic_v5_irs_cache_id_regs(const struct gic_kvm_info *info)
{
irs_caps.irs_base = info->gicv5_irs.base;
irs_caps.non_coherent = info->gicv5_irs.non_coherent;
irs_caps.idr2 = irs_readl_relaxed(GICV5_IRS_IDR2);
irs_caps.idr3 = irs_readl_relaxed(GICV5_IRS_IDR3);
irs_caps.idr4 = irs_readl_relaxed(GICV5_IRS_IDR4);
}
/*
* Probe for a vGICv5 compatible interrupt controller, returning 0 on success.
*/
@ -60,10 +76,12 @@ int vgic_v5_probe(const struct gic_kvm_info *info)
goto skip_v5;
}
kvm_vgic_global_state.max_gic_vcpus = VGIC_V5_MAX_CPUS;
vgic_v5_irs_cache_id_regs(info);
vgic_v5_get_implemented_ppis();
kvm_vgic_global_state.max_gic_vcpus = min(vgic_v5_irs_max_vpes(&irs_caps),
VGIC_V5_MAX_CPUS);
ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V5);
if (ret) {
kvm_err("Cannot register GICv5 KVM device.\n");

75
include/kvm/arm_vgic.h
View File

@ -132,6 +132,19 @@ enum vgic_type {
VGIC_V5, /* Newer, fancier GICv5 */
};
struct vgic_v5_irs_caps {
/* Base address of the host IRS's CONFIG_FRAME */
void __iomem *irs_base;
/* Raw host IRS ID registers */
u32 idr2;
u32 idr3;
u32 idr4;
/* Is the IRS coherent with us, or not? */
bool non_coherent;
};
/* same for all guests, as depending only on the _host's_ GIC model */
struct vgic_global {
/* type of the host GIC */
@ -182,6 +195,9 @@ struct vgic_global {
struct {
DECLARE_BITMAP(impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS);
} vgic_v5_ppi_caps;
/* GICv5 IRS capabilities */
struct vgic_v5_irs_caps vgic_v5_irs_caps;
};
extern struct vgic_global kvm_vgic_global_state;
@ -627,6 +643,65 @@ int vgic_v4_load(struct kvm_vcpu *vcpu);
void vgic_v4_commit(struct kvm_vcpu *vcpu);
int vgic_v4_put(struct kvm_vcpu *vcpu);
static inline u8 vgic_v5_irs_ist_id_bits(const struct vgic_v5_irs_caps *caps)
{
return FIELD_GET(GICV5_IRS_IDR2_ID_BITS, caps->idr2);
}
static inline u8 vgic_v5_irs_min_lpi_id_bits(const struct vgic_v5_irs_caps *caps)
{
return FIELD_GET(GICV5_IRS_IDR2_MIN_LPI_ID_BITS, caps->idr2);
}
static inline bool vgic_v5_irs_ist_levels(const struct vgic_v5_irs_caps *caps)
{
return !!(caps->idr2 & GICV5_IRS_IDR2_IST_LEVELS);
}
static inline u8 vgic_v5_irs_ist_l2sz(const struct vgic_v5_irs_caps *caps)
{
return FIELD_GET(GICV5_IRS_IDR2_IST_L2SZ, caps->idr2);
}
static inline bool vgic_v5_irs_istmd(const struct vgic_v5_irs_caps *caps)
{
return !!(caps->idr2 & GICV5_IRS_IDR2_ISTMD);
}
static inline u8 vgic_v5_irs_istmd_sz(const struct vgic_v5_irs_caps *caps)
{
return FIELD_GET(GICV5_IRS_IDR2_ISTMD_SZ, caps->idr2);
}
static inline u32 vgic_v5_irs_max_vms(const struct vgic_v5_irs_caps *caps)
{
return BIT(FIELD_GET(GICV5_IRS_IDR3_VM_ID_BITS, caps->idr3));
}
static inline bool vgic_v5_irs_two_level_vmt_support(const struct vgic_v5_irs_caps *caps)
{
return !!(caps->idr3 & GICV5_IRS_IDR3_VMT_LEVELS);
}
static inline u16 vgic_v5_irs_vmd_size(const struct vgic_v5_irs_caps *caps)
{
if (!(caps->idr3 & GICV5_IRS_IDR3_VMD))
return 0;
return BIT(FIELD_GET(GICV5_IRS_IDR3_VMD_SZ, caps->idr3));
}
static inline u16 vgic_v5_irs_vped_size(const struct vgic_v5_irs_caps *caps)
{
return BIT(FIELD_GET(GICV5_IRS_IDR4_VPED_SZ, caps->idr4));
}
static inline u32 vgic_v5_irs_max_vpes(const struct vgic_v5_irs_caps *caps)
{
/* Field stores VPE_ID_BITS - 1 */
return BIT(FIELD_GET(GICV5_IRS_IDR4_VPE_ID_BITS, caps->idr4) + 1);
}
int vgic_v5_finalize_ppi_state(struct kvm *kvm);
bool vgic_v5_ppi_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
unsigned long flags);