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drm/xe: Mark BCS engines as belonging to the GT forcewake domain

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On all platforms supported by the Xe driver, BCS engines are part of the
GT forcewake domain, not the RENDER domain.  Fix the engine list
definition to match the spec.  This mistake didn't really cause any
real problems because the forcewake domain here was only used in a
couple assertions that aren't really necessary and included in the
information dumped during error capture.

Bspec: 66696, 66534, 67609, 71185, 74417, 75242, 78286
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260424-engine-setup-v2-10-59cc620a25f1@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Matt Roper 2026-04-24 13:48:20 -07:00
parent cd2f1b4462
commit 8954033df4
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/drm/xe/xe_hw_engine.c
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@ -67,7 +67,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.instance = 0,
.irq_offset = ilog2(INTR_BCS(0)),
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = BLT_RING_BASE,
},
[XE_HW_ENGINE_BCS1] = {
@ -75,7 +75,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.instance = 1,
.irq_offset = ilog2(INTR_BCS(1)),
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = XEHPC_BCS1_RING_BASE,
},
[XE_HW_ENGINE_BCS2] = {
@ -83,7 +83,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.instance = 2,
.irq_offset = ilog2(INTR_BCS(2)),
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = XEHPC_BCS2_RING_BASE,
},
[XE_HW_ENGINE_BCS3] = {
@ -91,7 +91,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.instance = 3,
.irq_offset = ilog2(INTR_BCS(3)),
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = XEHPC_BCS3_RING_BASE,
},
[XE_HW_ENGINE_BCS4] = {
@ -99,7 +99,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.instance = 4,
.irq_offset = ilog2(INTR_BCS(4)),
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = XEHPC_BCS4_RING_BASE,
},
[XE_HW_ENGINE_BCS5] = {
@ -107,7 +107,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.instance = 5,
.irq_offset = ilog2(INTR_BCS(5)),
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = XEHPC_BCS5_RING_BASE,
},
[XE_HW_ENGINE_BCS6] = {
@ -115,7 +115,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.instance = 6,
.irq_offset = ilog2(INTR_BCS(6)),
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = XEHPC_BCS6_RING_BASE,
},
[XE_HW_ENGINE_BCS7] = {
@ -123,7 +123,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.irq_offset = ilog2(INTR_BCS(7)),
.instance = 7,
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = XEHPC_BCS7_RING_BASE,
},
[XE_HW_ENGINE_BCS8] = {
@ -131,7 +131,7 @@ static const struct engine_info engine_infos[] = {
.class = XE_ENGINE_CLASS_COPY,
.instance = 8,
.irq_offset = ilog2(INTR_BCS8),
.domain = XE_FW_RENDER,
.domain = XE_FW_GT,
.mmio_base = XEHPC_BCS8_RING_BASE,
},