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arm64: dts: renesas: r9a09g087: Add MTU3 support

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The Renesas RZ/N2H (R9A09G087) SoC has an MTU3 block.

Add support for it.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260410163530.383818-11-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Cosmin Tanislav 2026-04-10 19:35:30 +03:00 committed by Geert Uytterhoeven
parent f7abc1cf24
commit 893227dea7
1 changed files with 68 additions and 0 deletions
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68
arch/arm64/boot/dts/renesas/r9a09g087.dtsi
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@ -1119,6 +1119,74 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
mtu3: timer@90001200 {
compatible = "renesas,r9a09g087-mtu3",
"renesas,rz-mtu3";
reg = <0 0x90001200 0 0xb00>;
interrupts = <GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 421 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 422 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 425 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 427 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 428 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 429 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 430 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 441 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 446 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 447 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 449 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 450 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 451 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 452 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 453 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 454 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 455 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 458 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 460 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
"tciv0", "tgie0", "tgif0",
"tgia1", "tgib1", "tciv1", "tciu1",
"tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
"tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
"tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
"tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
"tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
"tciv8";
clocks = <&cpg CPG_MOD 200>;
power-domains = <&cpg>;
#pwm-cells = <3>;
status = "disabled";
};
adc0: adc@90014000 {
compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc";
reg = <0 0x90014000 0 0x400>;