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powerpc: Prepare for IRQ entry exit
Move interrupt entry and exit helper routines from interrupt.h into the PowerPC-specific entry-common.h header as a preparatory step for enabling the generic entry/exit framework. This consolidation places all PowerPC interrupt entry/exit handling in a single common header, aligning with the generic entry infrastructure. The helpers provide architecture-specific handling for interrupt and NMI entry/exit sequences, including: - arch_interrupt_enter/exit_prepare() - arch_interrupt_async_enter/exit_prepare() - arch_interrupt_nmi_enter/exit_prepare() - Supporting helpers such as nap_adjust_return(), check_return_regs_valid(), debug register maintenance, and soft mask handling. The functions are copied verbatim from interrupt.h.Subsequent patches will integrate these routines into the generic entry/exit flow. No functional change intended. Signed-off-by: Mukesh Kumar Chaurasiya <mchauras@linux.ibm.com> Tested-by: Samir M <samir@linux.ibm.com> Tested-by: David Gow <davidgow@google.com> Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com> Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Link: https://patch.msgid.link/20260427122742.210074-7-mkchauras@gmail.com
This commit is contained in:
Mukesh Kumar Chaurasiya
Madhavan Srinivasan
parent
d7a6797e0b
commit
893082ac76
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@ -5,10 +5,75 @@
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#include <asm/cputime.h>
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#include <asm/interrupt.h>
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#include <asm/runlatch.h>
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#include <asm/stacktrace.h>
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#include <asm/switch_to.h>
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#include <asm/tm.h>
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#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
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/*
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* WARN/BUG is handled with a program interrupt so minimise checks here to
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* avoid recursion and maximise the chance of getting the first oops handled.
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*/
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#define INT_SOFT_MASK_BUG_ON(regs, cond) \
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do { \
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if ((user_mode(regs) || (TRAP(regs) != INTERRUPT_PROGRAM))) \
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BUG_ON(cond); \
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} while (0)
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#else
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#define INT_SOFT_MASK_BUG_ON(regs, cond)
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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extern char __end_soft_masked[];
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bool search_kernel_soft_mask_table(unsigned long addr);
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unsigned long search_kernel_restart_table(unsigned long addr);
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DECLARE_STATIC_KEY_FALSE(interrupt_exit_not_reentrant);
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static inline bool is_implicit_soft_masked(struct pt_regs *regs)
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{
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if (user_mode(regs))
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return false;
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if (regs->nip >= (unsigned long)__end_soft_masked)
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return false;
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return search_kernel_soft_mask_table(regs->nip);
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}
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static inline void srr_regs_clobbered(void)
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{
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local_paca->srr_valid = 0;
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local_paca->hsrr_valid = 0;
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}
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#else
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static inline unsigned long search_kernel_restart_table(unsigned long addr)
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{
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return 0;
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}
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static inline bool is_implicit_soft_masked(struct pt_regs *regs)
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{
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return false;
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}
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static inline void srr_regs_clobbered(void)
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{
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}
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#endif
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static inline void nap_adjust_return(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC_970_NAP
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if (unlikely(test_thread_local_flags(_TLF_NAPPING))) {
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/* Can avoid a test-and-clear because NMIs do not call this */
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clear_thread_local_flags(_TLF_NAPPING);
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regs_set_return_ip(regs, (unsigned long)power4_idle_nap_return);
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}
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#endif
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}
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static __always_inline void booke_load_dbcr0(void)
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{
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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@ -31,6 +96,299 @@ static __always_inline void booke_load_dbcr0(void)
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#endif
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}
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static inline void booke_restore_dbcr0(void)
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{
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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unsigned long dbcr0 = current->thread.debug.dbcr0;
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if (IS_ENABLED(CONFIG_PPC32) && unlikely(dbcr0 & DBCR0_IDM)) {
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mtspr(SPRN_DBSR, -1);
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mtspr(SPRN_DBCR0, global_dbcr0[smp_processor_id()]);
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}
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#endif
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}
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static inline void check_return_regs_valid(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC_BOOK3S_64
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unsigned long trap, srr0, srr1;
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static bool warned;
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u8 *validp;
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char *h;
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if (trap_is_scv(regs))
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return;
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trap = TRAP(regs);
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// EE in HV mode sets HSRRs like 0xea0
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if (cpu_has_feature(CPU_FTR_HVMODE) && trap == INTERRUPT_EXTERNAL)
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trap = 0xea0;
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switch (trap) {
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case 0x980:
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case INTERRUPT_H_DATA_STORAGE:
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case 0xe20:
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case 0xe40:
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case INTERRUPT_HMI:
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case 0xe80:
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case 0xea0:
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case INTERRUPT_H_FAC_UNAVAIL:
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case 0x1200:
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case 0x1500:
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case 0x1600:
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case 0x1800:
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validp = &local_paca->hsrr_valid;
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if (!READ_ONCE(*validp))
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return;
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srr0 = mfspr(SPRN_HSRR0);
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srr1 = mfspr(SPRN_HSRR1);
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h = "H";
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break;
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default:
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validp = &local_paca->srr_valid;
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if (!READ_ONCE(*validp))
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return;
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srr0 = mfspr(SPRN_SRR0);
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srr1 = mfspr(SPRN_SRR1);
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h = "";
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break;
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}
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if (srr0 == regs->nip && srr1 == regs->msr)
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return;
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/*
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* A NMI / soft-NMI interrupt may have come in after we found
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* srr_valid and before the SRRs are loaded. The interrupt then
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* comes in and clobbers SRRs and clears srr_valid. Then we load
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* the SRRs here and test them above and find they don't match.
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*
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* Test validity again after that, to catch such false positives.
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*
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* This test in general will have some window for false negatives
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* and may not catch and fix all such cases if an NMI comes in
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* later and clobbers SRRs without clearing srr_valid, but hopefully
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* such things will get caught most of the time, statistically
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* enough to be able to get a warning out.
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*/
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if (!READ_ONCE(*validp))
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return;
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if (!data_race(warned)) {
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data_race(warned = true);
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pr_warn("%sSRR0 was: %lx should be: %lx\n", h, srr0, regs->nip);
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pr_warn("%sSRR1 was: %lx should be: %lx\n", h, srr1, regs->msr);
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show_regs(regs);
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}
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WRITE_ONCE(*validp, 0); /* fixup */
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#endif
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}
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static inline void arch_interrupt_enter_prepare(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC64
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irq_soft_mask_set(IRQS_ALL_DISABLED);
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/*
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* If the interrupt was taken with HARD_DIS clear, then enable MSR[EE].
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* Asynchronous interrupts get here with HARD_DIS set (see below), so
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* this enables MSR[EE] for synchronous interrupts. IRQs remain
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* soft-masked. The interrupt handler may later call
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* interrupt_cond_local_irq_enable() to achieve a regular process
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* context.
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*/
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if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) {
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INT_SOFT_MASK_BUG_ON(regs, !(regs->msr & MSR_EE));
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__hard_irq_enable();
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} else {
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__hard_RI_enable();
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}
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/* Enable MSR[RI] early, to support kernel SLB and hash faults */
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#endif
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if (!regs_irqs_disabled(regs))
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trace_hardirqs_off();
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if (user_mode(regs)) {
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kuap_lock();
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account_cpu_user_entry();
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account_stolen_time();
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} else {
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kuap_save_and_lock(regs);
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/*
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* CT_WARN_ON comes here via program_check_exception,
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* so avoid recursion.
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*/
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if (TRAP(regs) != INTERRUPT_PROGRAM)
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CT_WARN_ON(ct_state() != CT_STATE_KERNEL &&
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ct_state() != CT_STATE_IDLE);
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INT_SOFT_MASK_BUG_ON(regs, is_implicit_soft_masked(regs));
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INT_SOFT_MASK_BUG_ON(regs, regs_irqs_disabled(regs) &&
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search_kernel_restart_table(regs->nip));
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}
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INT_SOFT_MASK_BUG_ON(regs, !regs_irqs_disabled(regs) &&
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!(regs->msr & MSR_EE));
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booke_restore_dbcr0();
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}
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/*
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* Care should be taken to note that arch_interrupt_exit_prepare and
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* arch_interrupt_async_exit_prepare do not necessarily return immediately to
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* regs context (e.g., if regs is usermode, we don't necessarily return to
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* user mode). Other interrupts might be taken between here and return,
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* context switch / preemption may occur in the exit path after this, or a
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* signal may be delivered, etc.
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*
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* The real interrupt exit code is platform specific, e.g.,
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* interrupt_exit_user_prepare / interrupt_exit_kernel_prepare for 64s.
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*
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* However arch_interrupt_nmi_exit_prepare does return directly to regs, because
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* NMIs do not do "exit work" or replay soft-masked interrupts.
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*/
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static inline void arch_interrupt_exit_prepare(struct pt_regs *regs)
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{
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if (user_mode(regs)) {
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BUG_ON(regs_is_unrecoverable(regs));
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BUG_ON(regs_irqs_disabled(regs));
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/*
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* We don't need to restore AMR on the way back to userspace for KUAP.
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* AMR can only have been unlocked if we interrupted the kernel.
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*/
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kuap_assert_locked();
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local_irq_disable();
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}
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}
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static inline void arch_interrupt_async_enter_prepare(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC64
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/* Ensure arch_interrupt_enter_prepare does not enable MSR[EE] */
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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#endif
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arch_interrupt_enter_prepare(regs);
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* RI=1 is set by arch_interrupt_enter_prepare, so this thread flags access
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* has to come afterward (it can cause SLB faults).
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*/
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if (cpu_has_feature(CPU_FTR_CTRL) &&
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!test_thread_local_flags(_TLF_RUNLATCH))
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__ppc64_runlatch_on();
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#endif
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}
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static inline void arch_interrupt_async_exit_prepare(struct pt_regs *regs)
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{
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/*
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* Adjust at exit so the main handler sees the true NIA. This must
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* come before irq_exit() because irq_exit can enable interrupts, and
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* if another interrupt is taken before nap_adjust_return has run
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* here, then that interrupt would return directly to idle nap return.
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*/
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nap_adjust_return(regs);
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arch_interrupt_exit_prepare(regs);
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}
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struct interrupt_nmi_state {
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#ifdef CONFIG_PPC64
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u8 irq_soft_mask;
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u8 irq_happened;
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u8 ftrace_enabled;
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u64 softe;
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#endif
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};
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static inline bool nmi_disables_ftrace(struct pt_regs *regs)
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{
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/* Allow DEC and PMI to be traced when they are soft-NMI */
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if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) {
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if (TRAP(regs) == INTERRUPT_DECREMENTER)
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return false;
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if (TRAP(regs) == INTERRUPT_PERFMON)
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return false;
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}
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if (IS_ENABLED(CONFIG_PPC_BOOK3E_64)) {
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if (TRAP(regs) == INTERRUPT_PERFMON)
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return false;
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}
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return true;
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}
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static inline void arch_interrupt_nmi_enter_prepare(struct pt_regs *regs,
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struct interrupt_nmi_state *state)
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{
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#ifdef CONFIG_PPC64
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state->irq_soft_mask = local_paca->irq_soft_mask;
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state->irq_happened = local_paca->irq_happened;
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state->softe = regs->softe;
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/*
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* Set IRQS_ALL_DISABLED unconditionally so irqs_disabled() does
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* the right thing, and set IRQ_HARD_DIS. We do not want to reconcile
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* because that goes through irq tracing which we don't want in NMI.
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*/
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local_paca->irq_soft_mask = IRQS_ALL_DISABLED;
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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if (!(regs->msr & MSR_EE) || is_implicit_soft_masked(regs)) {
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/*
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* Adjust regs->softe to be soft-masked if it had not been
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* reconcied (e.g., interrupt entry with MSR[EE]=0 but softe
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* not yet set disabled), or if it was in an implicit soft
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* masked state. This makes regs_irqs_disabled(regs)
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* behave as expected.
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*/
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regs->softe = IRQS_ALL_DISABLED;
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}
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__hard_RI_enable();
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/* Don't do any per-CPU operations until interrupt state is fixed */
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if (nmi_disables_ftrace(regs)) {
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state->ftrace_enabled = this_cpu_get_ftrace_enabled();
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this_cpu_set_ftrace_enabled(0);
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}
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#endif
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}
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static inline void arch_interrupt_nmi_exit_prepare(struct pt_regs *regs,
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struct interrupt_nmi_state *state)
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{
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/*
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* nmi does not call nap_adjust_return because nmi should not create
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* new work to do (must use irq_work for that).
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*/
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#ifdef CONFIG_PPC64
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#ifdef CONFIG_PPC_BOOK3S
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if (regs_irqs_disabled(regs)) {
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unsigned long rst = search_kernel_restart_table(regs->nip);
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if (rst)
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regs_set_return_ip(regs, rst);
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}
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#endif
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if (nmi_disables_ftrace(regs))
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this_cpu_set_ftrace_enabled(state->ftrace_enabled);
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/* Check we didn't change the pending interrupt mask. */
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WARN_ON_ONCE((state->irq_happened | PACA_IRQ_HARD_DIS) != local_paca->irq_happened);
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regs->softe = state->softe;
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local_paca->irq_happened = state->irq_happened;
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local_paca->irq_soft_mask = state->irq_soft_mask;
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#endif
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}
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static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs)
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{
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kuap_lock();
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