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platform/x86/amd/hsmp: Document and expose client telemetry table in UAPI
Add struct hsmp_telemetry_table_rm to the UAPI header, describing the Ryzen Master SMC telemetry table (table version 5, as reported by HSMP_CLIENT_GET_METRICS_TABLE_VER) returned by HSMP_CLIENT_GET_METRICS_TABLE on the Family 1Ah client models, now that the previous commit wires that message up to a usable DRAM mapping. Point amd_hsmp.rst at struct hsmp_telemetry_table_rm instead of duplicating the layout in prose. The Public PPR for the model in use remains the reference for units and encodings. Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Link: https://patch.msgid.link/20261012085407.1202295-5-muralidhara.mk@amd.com Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
This commit is contained in:
Muralidhara M K
Ilpo Järvinen
parent
3a48937306
commit
893018d51f
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@ -221,9 +221,23 @@ The following IOCTLs are defined:
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``sizeof(struct hsmp_metric_table)``. Later version metrics table
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layout is documented in the Public PPR.
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The Family 1Ah client models carry their own telemetry table instead,
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described in `Family 1Ah client telemetry table`_ below.
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The ioctl would return a non-zero on failure; you can read errno to see
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what happened. The transaction returns 0 on success.
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Family 1Ah client telemetry table
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=================================
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On the Family 1Ah client models, ``HSMP_CLIENT_GET_METRICS_TABLE`` (05h)
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returns the Ryzen Master SMC telemetry table, table version 5 as
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reported by ``HSMP_CLIENT_GET_METRICS_TABLE_VER`` (04h). This is the
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Telemetry Table RM layout, defined as ``struct hsmp_telemetry_table_rm``
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in amd_hsmp.h. The driver copies the table out without interpreting it.
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See the telemetry table chapter of the AMD Public PPR for the model in
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use for the units and encodings of its fields.
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More details on the interface and message definitions can be found in chapter
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"7 Host System Management Port (HSMP)" of the respective family/model PPR
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eg: https://docs.amd.com/v/u/en-US/55898_B1_pub_0_50
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@ -827,4 +827,261 @@ enum hsmp_client_message_ids {
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HSMP_CLIENT_MSG_ID_MAX,
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};
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#define HSMP_TELEMETRY_RM_MAX_CCX 4
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#define HSMP_TELEMETRY_RM_CORES_PER_CCX 12
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#define HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE 8
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#define HSMP_TELEMETRY_RM_NPU_BUSY_DOMAINS 3
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#define HSMP_TELEMETRY_RM_OC_DOMAINS 5
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#define HSMP_TELEMETRY_RM_OC_SUBDOMAINS 5
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#define HSMP_TELEMETRY_RM_OC_GUARDBANDS 3
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/* Firmware packs this table to a 4-byte boundary */
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#pragma pack(push, 4)
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/*
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* struct hsmp_telemetry_table_rm_iod - I/O die counters for RM telemetry.
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*
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* Accumulator (*_acc) fields are monotonic counters; consumers derive
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* deltas across two snapshots and normalise by accumulation_counter.
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*/
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struct hsmp_telemetry_table_rm_iod {
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__u32 accumulation_counter;
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/* SET VOLTAGES */
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__u64 vddcr_set_voltage;
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__u64 vddcr_soc_set_voltage;
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__u64 vddcr_npu_set_voltage;
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__u64 vddcr_lp_set_voltage;
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__u64 vddcr_gfx_set_voltage;
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__u64 vdd_misc_set_voltage;
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/* TELEMETRY VOLTAGES */
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__u64 vddcr_telemetry_voltage;
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__u64 vddcr_soc_telemetry_voltage;
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__u64 vddcr_npu_telemetry_voltage;
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__u64 vddcr_lp_telemetry_voltage;
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__u64 vddcr_gfx_telemetry_voltage;
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__u64 vdd_misc_telemetry_voltage;
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/* TELEMETRY POWERS */
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__u64 vddcr_telemetry_power;
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__u64 vddcr_soc_telemetry_power;
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__u64 vddcr_npu_telemetry_power;
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__u64 vddcr_lp_telemetry_power;
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__u64 vddcr_gfx_telemetry_power;
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__u64 vdd_misc_telemetry_power;
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/* THROTTLERS - FAST PPT */
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__u32 fppt_fused_limit;
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__u32 fppt_max_irm_limit;
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__u32 fppt_max_pbo_limit;
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__u32 fppt_limit;
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__u64 fppt_value_acc;
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__u32 fppt_residency_acc;
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/* THROTTLERS - SLOW PPT */
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__u32 sppt_fused_limit;
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__u32 sppt_max_irm_limit;
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__u32 sppt_max_pbo_limit;
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__u32 sppt_limit;
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__u64 sppt_value_acc;
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__u32 sppt_residency_acc;
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/* THROTTLERS - SPL */
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__u32 spl_fused_limit;
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__u32 spl_max_irm_limit;
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__u32 spl_max_pbo_limit;
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__u32 spl_limit;
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__u64 spl_value_acc;
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__u32 spl_residency_acc;
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/* THROTTLERS - TDC VDDCR */
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__u32 tdc_vddcr_fused_limit;
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__u32 tdc_vddcr_max_irm_limit;
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__u32 tdc_vddcr_max_pbo_limit;
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__u32 tdc_vddcr_limit;
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__u64 tdc_vddcr_value_acc;
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__u32 tdc_vddcr_residency_acc;
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/* THROTTLERS - TDC VDDCR SOC */
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__u32 tdc_vddcr_soc_fused_limit;
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__u32 tdc_vddcr_soc_max_irm_limit;
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__u32 tdc_vddcr_soc_max_pbo_limit;
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__u32 tdc_vddcr_soc_limit;
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__u64 tdc_vddcr_soc_value_acc;
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__u32 tdc_vddcr_soc_residency_acc;
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/* THROTTLERS - TDC VDDCR NPU */
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__u32 tdc_vddcr_npu_fused_limit;
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__u32 tdc_vddcr_npu_max_irm_limit;
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__u32 tdc_vddcr_npu_max_pbo_limit;
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__u32 tdc_vddcr_npu_limit;
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__u64 tdc_vddcr_npu_value_acc;
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__u32 tdc_vddcr_npu_residency_acc;
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/* THROTTLERS - TDC VDDCR LP */
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__u32 tdc_vddcr_lp_fused_limit;
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__u32 tdc_vddcr_lp_max_irm_limit;
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__u32 tdc_vddcr_lp_max_pbo_limit;
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__u32 tdc_vddcr_lp_limit;
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__u64 tdc_vddcr_lp_value_acc;
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__u32 tdc_vddcr_lp_residency_acc;
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/* THROTTLERS - TDC VDDCR GFX */
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__u32 tdc_vddcr_gfx_fused_limit;
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__u32 tdc_vddcr_gfx_max_irm_limit;
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__u32 tdc_vddcr_gfx_max_pbo_limit;
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__u32 tdc_vddcr_gfx_limit;
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__u64 tdc_vddcr_gfx_value_acc;
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__u32 tdc_vddcr_gfx_residency_acc;
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/* THROTTLERS - EDC VDDCR */
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__u32 edc_vddcr_fused_limit;
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__u32 edc_vddcr_max_irm_limit;
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__u32 edc_vddcr_max_pbo_limit;
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__u32 edc_vddcr_limit;
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/* THROTTLERS - THERMAL */
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__u32 thm_fused_limit;
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__u32 thm_limit;
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__u64 thm_value_acc;
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__u32 thm_residency_acc;
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__u32 prochot_residency_acc;
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__u64 gfx_temp_acc;
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__u64 soc_temp_acc;
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__u32 p3t_fused_limit;
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__u64 p3t_value_acc;
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/* POWER */
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__u64 system_power_acc;
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__u64 apu_power_acc;
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__u64 dgpu_power_acc;
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__u64 npu_power_acc;
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/* FREQUENCIES */
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__u64 fclk_freq_eff_acc;
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__u64 memclk_freq_eff_acc;
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__u64 lclk_freq_eff_acc;
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__u64 gfxclk_freq_eff_acc;
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__u64 socclk_freq_eff_acc;
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__u64 vclk_freq_eff_acc;
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__u64 vpeclk_freq_eff_acc;
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__u64 aieclk_freq_eff_acc;
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__u64 npuhclk_freq_eff_acc;
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/* BANDWIDTH */
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__u64 dram_read_bandwidth;
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__u64 dram_write_bandwidth;
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/* ACTIVITY MONITORS */
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__u64 gfx_busy_acc;
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__u64 vcn_busy_acc;
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__u64 npu_busy_acc[HSMP_TELEMETRY_RM_NPU_BUSY_DOMAINS];
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/* STT (Skin Temperature Tracking) */
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__u32 stt_min_limit;
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__u64 stt_apu_hot_spot_temp_acc;
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__u64 stt_hs2_hot_spot_temp_acc;
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__u32 stt_apu_temp_limit;
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__u64 stt_apu_skin_temp_acc;
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/* RESIDENCIES - per-CCX CPU off */
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__u64 cpu_off_residency[HSMP_TELEMETRY_RM_MAX_CCX];
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/* DF P-STATES */
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__u32 fclk_freq_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE];
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__u32 uclk_freq_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE];
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__u32 ddr_rate_table[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE];
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__u8 df_pstate_source[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE];
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/* SYSTEM */
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__u8 gfx_disabled;
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__u8 spare2[3];
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__u32 gfxclk_fmax;
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__u8 cclk_core_fuse_enable[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_CORES_PER_CCX];
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__u8 cclk_core_enabled[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_CORES_PER_CCX];
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__u32 cclk_fmax[HSMP_TELEMETRY_RM_MAX_CCX][HSMP_TELEMETRY_RM_CORES_PER_CCX];
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/* OVERCLOCK CAPABLE */
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__u8 cpu_precise_and_direct_oc_capable;
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__u8 gfx_precise_and_direct_oc_capable;
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__u8 pbo_basic_oc_capable;
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__u8 pbo_advanced_oc_capable;
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__u8 pbo_nitro_oc_capable;
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__u8 memory_and_fabric_oc_capable;
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__u8 misc_oc_capable;
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__u8 extreme_cold_oc_capable;
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__u8 down_config_control_capable;
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__u8 spare0[3];
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/* OVERCLOCK STATUS */
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__u32 fit_limit_scalar;
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__u8 ln2_enabled;
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__u8 cpu_precise_and_direct_oc_enabled;
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__u8 gfx_precise_and_direct_oc_enabled;
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__u8 spare1[2];
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__s8 psm_guardband[HSMP_TELEMETRY_RM_OC_DOMAINS]
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[HSMP_TELEMETRY_RM_OC_SUBDOMAINS]
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[HSMP_TELEMETRY_RM_OC_GUARDBANDS];
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__s32 core_power_limit_offset;
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__u32 max_freq_offset[HSMP_TELEMETRY_RM_OC_DOMAINS];
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__u64 npu_temp_acc;
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__u64 df_pstate_residency_acc[HSMP_TELEMETRY_RM_FREQ_TABLE_SIZE];
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__u32 cclk_fboost;
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/* PMF */
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__u32 pmf_fast_apu_ppt_limit;
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__u64 pmf_fast_apu_ppt_value_acc;
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__u32 pmf_fast_apu_ppt_residency_acc;
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__u32 pmf_slow_apu_ppt_limit;
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__u64 pmf_slow_apu_ppt_value_acc;
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__u32 pmf_slow_apu_ppt_residency_acc;
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__u32 pmf_fast_spm_limit;
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__u64 pmf_fast_spm_value_acc;
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__u32 pmf_fast_spm_residency_acc;
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__u32 pmf_slow_spm_limit;
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__u64 pmf_slow_spm_value_acc;
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__u32 pmf_slow_spm_residency_acc;
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__u32 spare3[5];
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};
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/*
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* struct hsmp_telemetry_table_rm_ccx - Per-CCX core counters for RM telemetry.
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*
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* Arrays are sized for the maximum cores per CCX; use the
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* cclk_core_enabled[] mask in struct hsmp_telemetry_table_rm_iod to tell
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* which entries are valid.
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*/
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struct hsmp_telemetry_table_rm_ccx {
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__u64 core_c0[HSMP_TELEMETRY_RM_CORES_PER_CCX];
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__u64 core_cc6[HSMP_TELEMETRY_RM_CORES_PER_CCX];
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__u64 core_freq[HSMP_TELEMETRY_RM_CORES_PER_CCX];
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__u64 core_freq_eff[HSMP_TELEMETRY_RM_CORES_PER_CCX];
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__u64 core_temp[HSMP_TELEMETRY_RM_CORES_PER_CCX];
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__u64 core_power[HSMP_TELEMETRY_RM_CORES_PER_CCX];
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};
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/**
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* struct hsmp_telemetry_table_rm - Top-level RM telemetry table.
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* @iod: I/O die counters and per-rail/per-throttler/SYSTEM telemetry.
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* @ccx: Per-CCX core counters, one entry per CCX.
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*
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* Layout of the table returned by HSMP_CLIENT_GET_METRICS_TABLE on the
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* Family 1Ah client (Models 80h-8Fh and E0h-E3h), reported as table
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* version 5 by HSMP_CLIENT_GET_METRICS_TABLE_VER. Units are
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* firmware-defined; see the AMD HSMP/Ryzen Master SMC spec. Spare
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* fields are firmware padding and must be preserved.
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*/
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struct hsmp_telemetry_table_rm {
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struct hsmp_telemetry_table_rm_iod iod;
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struct hsmp_telemetry_table_rm_ccx ccx[HSMP_TELEMETRY_RM_MAX_CCX];
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};
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#pragma pack(pop)
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#endif /*_ASM_X86_AMD_HSMP_H_*/
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