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dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt type encoding

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The QUICC Engine port interrupt controller can be configured to generate
an interrupt on either a high-to-low transition or any change in the
signal state on the related GPIOs.

Update the #interrupt-cells property to 2 so consumers can encode
interrupt level information.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-2-1972044cfbd1@bootlin.com
Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
This commit is contained in:
Paul Louvel 2026-07-08 12:15:15 +02:00 committed by Christophe Leroy (CS GROUP)
parent 7e47fe5641
commit 890af4d046
1 changed files with 2 additions and 2 deletions
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4
Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml
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@ -23,7 +23,7 @@ properties:
const: 0
'#interrupt-cells':
const: 1
const: 2
interrupts:
maxItems: 1
@ -45,7 +45,7 @@ examples:
reg = <0xc00 0x18>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
interrupts = <74 0x8>;
interrupt-parent = <&ipic>;
};