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mtd: rawnand: sunxi: Add support for H616 nand controller
The H616 nand controller has the same base as A10/A23, with some differences: - mdma is based on chained buffers - its ECC supports up to 80bit per 1024bytes - some registers layouts are a bit different, mainly due do the stronger ECC. - it uses USER_DATA_LEN registers along USER_DATA registers. - it needs a specific clock for ECC and MBUS. Introduce the basic support, with ECC and scrambling, but without DMA/MDMA. Tested on Whatsminer H616 board (with and without scrambling, ECC) Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Richard Genoud
Miquel Raynal
parent
5ddfbc68ec
commit
88fd4e4dea
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@ -49,17 +49,40 @@
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#define NFC_REG_A23_IO_DATA 0x0300
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#define NFC_REG_ECC_CTL 0x0034
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#define NFC_REG_ECC_ST 0x0038
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#define NFC_REG_DEBUG 0x003C
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#define NFC_REG_H6_PAT_FOUND 0x003C
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#define NFC_REG_A10_ECC_ERR_CNT 0x0040
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#define NFC_REG_H6_ECC_ERR_CNT 0x0050
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#define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & ~0x3)
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#define NFC_REG_H6_RDATA_CTL 0x0044
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#define NFC_REG_H6_RDATA_0 0x0048
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#define NFC_REG_H6_RDATA_1 0x004C
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#define NFC_REG_A10_USER_DATA 0x0050
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#define NFC_REG_H6_USER_DATA 0x0080
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#define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4))
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#define NFC_REG_H6_USER_DATA_LEN 0x0070
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/* A USER_DATA_LEN register can hold the length of 8 USER_DATA registers */
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#define NFC_REG_USER_DATA_LEN_CAPACITY 8
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#define NFC_REG_USER_DATA_LEN(nfc, step) \
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(nfc->caps->reg_user_data_len + \
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((step) / NFC_REG_USER_DATA_LEN_CAPACITY) * 4)
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#define NFC_REG_SPARE_AREA(nfc) (nfc->caps->reg_spare_area)
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#define NFC_REG_A10_SPARE_AREA 0x00A0
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#define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id)
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#define NFC_REG_A10_PAT_ID 0x00A4
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#define NFC_REG_MDMA_ADDR 0x00C0
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#define NFC_REG_MDMA_CNT 0x00C4
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#define NFC_REG_H6_EFNAND_STATUS 0x0110
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#define NFC_REG_H6_SPARE_AREA 0x0114
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#define NFC_REG_H6_PAT_ID 0x0118
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#define NFC_REG_H6_DDR2_SPEC_CTL 0x011C
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#define NFC_REG_H6_NDMA_MODE_CTL 0x0120
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#define NFC_REG_H6_MDMA_DLBA_REG 0x0200
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#define NFC_REG_H6_MDMA_STA 0x0204
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#define NFC_REG_H6_MDMA_INT_MAS 0x0208
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#define NFC_REG_H6_MDMA_DESC_ADDR 0x020C
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#define NFC_REG_H6_MDMA_BUF_ADDR 0x0210
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#define NFC_REG_H6_MDMA_CNT 0x0214
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#define NFC_RAM0_BASE 0x0400
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#define NFC_RAM1_BASE 0x0800
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@ -71,6 +94,7 @@
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#define NFC_BUS_WIDTH_16 (1 << 2)
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#define NFC_RB_SEL_MSK BIT(3)
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#define NFC_RB_SEL(x) ((x) << 3)
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/* CE_SEL BIT 27 is meant to be used for GPIO chipselect */
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#define NFC_CE_SEL_MSK GENMASK(26, 24)
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#define NFC_CE_SEL(x) ((x) << 24)
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#define NFC_CE_CTL BIT(6)
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@ -89,6 +113,9 @@
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#define NFC_STA BIT(4)
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#define NFC_NATCH_INT_FLAG BIT(5)
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#define NFC_RB_STATE(x) BIT(x + 8)
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#define NFC_RB_STATE_MSK GENMASK(11, 8)
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#define NDFC_RDATA_STA_1 BIT(12)
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#define NDFC_RDATA_STA_0 BIT(13)
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/* define bit use in NFC_INT */
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#define NFC_B2R_INT_ENABLE BIT(0)
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@ -100,6 +127,7 @@
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/* define bit use in NFC_TIMING_CTL */
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#define NFC_TIMING_CTL_EDO BIT(8)
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#define NFC_TIMING_CTL_E_EDO BIT(9)
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/* define NFC_TIMING_CFG register layout */
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#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
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@ -107,9 +135,15 @@
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(((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
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(((tCAD) & 0x7) << 8))
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#define NFC_TIMING_CFG2(tCDQSS, tSC, tCLHZ, tCSS, tWC) \
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((((tCDQSS) & 0x1) << 11) | (((tSC) & 0x3) << 12) | \
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(((tCLHZ) & 0x3) << 14) | (((tCSS) & 0x3) << 16) | \
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(((tWC) & 0x3) << 18))
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/* define bit use in NFC_CMD */
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#define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
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#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
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#define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) /* 15-10 reserved on H6 */
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#define NFC_CMD_ADR_NUM_MSK GENMASK(9, 8)
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#define NFC_CMD(x) (x)
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#define NFC_ADR_NUM_MSK GENMASK(18, 16)
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#define NFC_ADR_NUM(x) (((x) - 1) << 16)
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@ -122,6 +156,7 @@
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#define NFC_SEQ BIT(25)
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#define NFC_DATA_SWAP_METHOD BIT(26)
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#define NFC_ROW_AUTO_INC BIT(27)
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#define NFC_H6_SEND_RND_CMD2 BIT(27)
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#define NFC_SEND_CMD3 BIT(28)
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#define NFC_SEND_CMD4 BIT(29)
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#define NFC_CMD_TYPE_MSK GENMASK(31, 30)
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@ -133,6 +168,7 @@
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#define NFC_READ_CMD_MSK GENMASK(7, 0)
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#define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
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#define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
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#define NFC_RND_READ_CMD2_MSK GENMASK(31, 24)
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/* define bit use in NFC_WCMD_SET */
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#define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
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@ -150,6 +186,9 @@
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#define NFC_RANDOM_DIRECTION(nfc) (nfc->caps->random_dir_mask)
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#define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask)
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#define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x))
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/* RANDOM_PAGE_SIZE: 0: ECC block size 1: page size */
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#define NFC_A23_RANDOM_PAGE_SIZE BIT(11)
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#define NFC_H6_RANDOM_PAGE_SIZE BIT(7)
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#define NFC_RANDOM_SEED_MSK GENMASK(30, 16)
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#define NFC_RANDOM_SEED(x) ((x) << 16)
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@ -165,6 +204,9 @@
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#define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff)
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#define NFC_USER_DATA_LEN_MSK(step) \
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(0xf << (((step) % NFC_REG_USER_DATA_LEN_CAPACITY) * 4))
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#define NFC_DEFAULT_TIMEOUT_MS 1000
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#define NFC_MAX_CS 7
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@ -235,9 +277,12 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
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* @has_mdma: Use mbus dma mode, otherwise general dma
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* through MBUS on A23/A33 needs extra configuration.
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* @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks
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* @has_ecc_clk: If the controller needs an ECC clock.
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* @has_mbus_clk: If the controller needs a mbus clock.
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* @reg_io_data: I/O data register
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* @reg_ecc_err_cnt: ECC error counter register
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* @reg_user_data: User data register
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* @reg_user_data_len: User data length register
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* @reg_spare_area: Spare Area Register
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* @reg_pat_id: Pattern ID Register
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* @reg_pat_found: Data Pattern Status Register
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@ -249,14 +294,24 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
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* @dma_maxburst: DMA maxburst
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* @ecc_strengths: Available ECC strengths array
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* @nstrengths: Size of @ecc_strengths
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* @max_ecc_steps: Maximum supported steps for ECC, this is also the
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* number of user data registers
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* @user_data_len_tab: Table of lenghts supported by USER_DATA_LEN register
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* The table index is the value to set in NFC_USER_DATA_LEN
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* registers, and the corresponding value is the number of
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* bytes to write
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* @nuser_data_tab: Size of @user_data_len_tab
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* @sram_size: Size of the NAND controller SRAM
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*/
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struct sunxi_nfc_caps {
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bool has_mdma;
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bool has_ecc_block_512;
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bool has_ecc_clk;
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bool has_mbus_clk;
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unsigned int reg_io_data;
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unsigned int reg_ecc_err_cnt;
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unsigned int reg_user_data;
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unsigned int reg_user_data_len;
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unsigned int reg_spare_area;
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unsigned int reg_pat_id;
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unsigned int reg_pat_found;
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@ -268,6 +323,9 @@ struct sunxi_nfc_caps {
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unsigned int dma_maxburst;
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const u8 *ecc_strengths;
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unsigned int nstrengths;
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const u8 *user_data_len_tab;
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unsigned int nuser_data_tab;
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unsigned int max_ecc_steps;
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int sram_size;
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};
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@ -279,6 +337,8 @@ struct sunxi_nfc_caps {
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* @regs: NAND controller registers
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* @ahb_clk: NAND controller AHB clock
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* @mod_clk: NAND controller mod clock
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* @ecc_clk: NAND controller ECC clock
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* @mbus_clk: NAND controller MBUS clock
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* @reset: NAND controller reset line
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* @assigned_cs: bitmask describing already assigned CS lines
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* @clk_rate: NAND controller current clock rate
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@ -294,6 +354,8 @@ struct sunxi_nfc {
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void __iomem *regs;
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struct clk *ahb_clk;
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struct clk *mod_clk;
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struct clk *ecc_clk;
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struct clk *mbus_clk;
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struct reset_control *reset;
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unsigned long assigned_cs;
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unsigned long clk_rate;
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@ -774,6 +836,53 @@ static void sunxi_nfc_hw_ecc_get_prot_oob_bytes(struct nand_chip *nand, u8 *oob,
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sunxi_nfc_randomize_bbm(nand, page, oob);
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}
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/*
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* On H6/H6 the user_data length has to be set in specific registers
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* before writing.
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*/
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static void sunxi_nfc_reset_user_data_len(struct sunxi_nfc *nfc)
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{
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int loop_step = NFC_REG_USER_DATA_LEN_CAPACITY;
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/* not all SoCs have this register */
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if (!nfc->caps->reg_user_data_len)
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return;
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for (int i = 0; i < nfc->caps->max_ecc_steps; i += loop_step)
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writel(0, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, i));
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}
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static void sunxi_nfc_set_user_data_len(struct sunxi_nfc *nfc,
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int len, int step)
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{
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bool found = false;
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u32 val;
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int i;
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/* not all SoCs have this register */
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if (!nfc->caps->reg_user_data_len)
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return;
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for (i = 0; i < nfc->caps->nuser_data_tab; i++) {
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if (len == nfc->caps->user_data_len_tab[i]) {
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found = true;
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break;
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}
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}
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if (!found) {
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dev_warn(nfc->dev,
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"Unsupported length for user data reg: %d\n", len);
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return;
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}
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val = readl(nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step));
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val &= ~NFC_USER_DATA_LEN_MSK(step);
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val |= field_prep(NFC_USER_DATA_LEN_MSK(step), i);
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writel(val, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step));
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}
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static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand,
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const u8 *oob, int step,
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bool bbm, int page)
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@ -868,6 +977,8 @@ static int sunxi_nfc_hw_ecc_read_chunk(struct nand_chip *nand,
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if (ret)
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return ret;
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sunxi_nfc_reset_user_data_len(nfc);
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sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0);
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sunxi_nfc_randomizer_config(nand, page, false);
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sunxi_nfc_randomizer_enable(nand);
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writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
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@ -978,6 +1089,8 @@ static int sunxi_nfc_hw_ecc_read_chunks_dma(struct nand_chip *nand, uint8_t *buf
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return ret;
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sunxi_nfc_hw_ecc_enable(nand);
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sunxi_nfc_reset_user_data_len(nfc);
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sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0);
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sunxi_nfc_randomizer_config(nand, page, false);
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sunxi_nfc_randomizer_enable(nand);
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@ -1110,6 +1223,8 @@ static int sunxi_nfc_hw_ecc_write_chunk(struct nand_chip *nand,
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sunxi_nfc_randomizer_config(nand, page, false);
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sunxi_nfc_randomizer_enable(nand);
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sunxi_nfc_reset_user_data_len(nfc);
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sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0);
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sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page);
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writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
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@ -1354,10 +1469,12 @@ static int sunxi_nfc_hw_ecc_write_page_dma(struct nand_chip *nand,
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if (ret)
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goto pio_fallback;
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sunxi_nfc_reset_user_data_len(nfc);
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for (i = 0; i < ecc->steps; i++) {
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const u8 *oob = nand->oob_poi + (i * (ecc->bytes + USER_DATA_SZ));
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sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page);
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sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, i);
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}
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nand_prog_page_begin_op(nand, page, 0, NULL, 0);
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@ -2158,6 +2275,10 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
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if (irq < 0)
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return irq;
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nfc->caps = of_device_get_match_data(dev);
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if (!nfc->caps)
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return -EINVAL;
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nfc->ahb_clk = devm_clk_get_enabled(dev, "ahb");
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if (IS_ERR(nfc->ahb_clk)) {
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dev_err(dev, "failed to retrieve ahb clk\n");
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@ -2170,6 +2291,22 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
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return PTR_ERR(nfc->mod_clk);
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}
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if (nfc->caps->has_ecc_clk) {
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nfc->ecc_clk = devm_clk_get_enabled(dev, "ecc");
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if (IS_ERR(nfc->ecc_clk)) {
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dev_err(dev, "failed to retrieve ecc clk\n");
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return PTR_ERR(nfc->ecc_clk);
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}
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}
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if (nfc->caps->has_mbus_clk) {
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nfc->mbus_clk = devm_clk_get_enabled(dev, "mbus");
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if (IS_ERR(nfc->mbus_clk)) {
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dev_err(dev, "failed to retrieve mbus clk\n");
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return PTR_ERR(nfc->mbus_clk);
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}
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}
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nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb");
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if (IS_ERR(nfc->reset))
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return PTR_ERR(nfc->reset);
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@ -2180,12 +2317,6 @@ static int sunxi_nfc_probe(struct platform_device *pdev)
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return ret;
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}
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nfc->caps = of_device_get_match_data(&pdev->dev);
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if (!nfc->caps) {
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ret = -EINVAL;
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goto out_ahb_reset_reassert;
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}
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ret = sunxi_nfc_rst(nfc);
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if (ret)
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goto out_ahb_reset_reassert;
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@ -2236,6 +2367,14 @@ static const u8 sunxi_ecc_strengths_a10[] = {
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16, 24, 28, 32, 40, 48, 56, 60, 64
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};
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static const u8 sunxi_ecc_strengths_h6[] = {
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16, 24, 28, 32, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80
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};
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static const u8 sunxi_user_data_len_h6[] = {
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0, 4, 8, 12, 16, 20, 24, 28, 32
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};
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static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
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.has_ecc_block_512 = true,
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.reg_io_data = NFC_REG_A10_IO_DATA,
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@ -2252,6 +2391,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = {
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.dma_maxburst = 4,
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.ecc_strengths = sunxi_ecc_strengths_a10,
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.nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_a10),
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.max_ecc_steps = 16,
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.sram_size = 1024,
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};
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@ -2272,9 +2412,34 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {
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.dma_maxburst = 8,
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||||
.ecc_strengths = sunxi_ecc_strengths_a10,
|
||||
.nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_a10),
|
||||
.max_ecc_steps = 16,
|
||||
.sram_size = 1024,
|
||||
};
|
||||
|
||||
static const struct sunxi_nfc_caps sunxi_nfc_h616_caps = {
|
||||
.has_ecc_clk = true,
|
||||
.has_mbus_clk = true,
|
||||
.reg_io_data = NFC_REG_A23_IO_DATA,
|
||||
.reg_ecc_err_cnt = NFC_REG_H6_ECC_ERR_CNT,
|
||||
.reg_user_data = NFC_REG_H6_USER_DATA,
|
||||
.reg_user_data_len = NFC_REG_H6_USER_DATA_LEN,
|
||||
.reg_spare_area = NFC_REG_H6_SPARE_AREA,
|
||||
.reg_pat_id = NFC_REG_H6_PAT_ID,
|
||||
.reg_pat_found = NFC_REG_H6_PAT_FOUND,
|
||||
.random_en_mask = BIT(5),
|
||||
.random_dir_mask = BIT(6),
|
||||
.ecc_mode_mask = GENMASK(15, 8),
|
||||
.ecc_err_mask = GENMASK(31, 0),
|
||||
.pat_found_mask = GENMASK(31, 0),
|
||||
.dma_maxburst = 8,
|
||||
.ecc_strengths = sunxi_ecc_strengths_h6,
|
||||
.nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_h6),
|
||||
.user_data_len_tab = sunxi_user_data_len_h6,
|
||||
.nuser_data_tab = ARRAY_SIZE(sunxi_user_data_len_h6),
|
||||
.max_ecc_steps = 32,
|
||||
.sram_size = 8192,
|
||||
};
|
||||
|
||||
static const struct of_device_id sunxi_nfc_ids[] = {
|
||||
{
|
||||
.compatible = "allwinner,sun4i-a10-nand",
|
||||
|
|
@ -2284,6 +2449,10 @@ static const struct of_device_id sunxi_nfc_ids[] = {
|
|||
.compatible = "allwinner,sun8i-a23-nand-controller",
|
||||
.data = &sunxi_nfc_a23_caps,
|
||||
},
|
||||
{
|
||||
.compatible = "allwinner,sun50i-h616-nand-controller",
|
||||
.data = &sunxi_nfc_h616_caps,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user