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drm/amd/ras: Add aca common ras functions
Add aca common ras functions: 1. Aca hw init/fini. 2. Get ecc count of each ras block. 3. Update query ecc count from mp1. 4. Clear ras block ecc count. V3: Update the calling function. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
YiPeng Chai
Alex Deucher
parent
fd98319f73
commit
88e379e5b8
672
drivers/gpu/drm/amd/ras/rascore/ras_aca.c
Normal file
672
drivers/gpu/drm/amd/ras/rascore/ras_aca.c
Normal file
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@ -0,0 +1,672 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "ras.h"
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#include "ras_aca.h"
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#include "ras_aca_v1_0.h"
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#include "ras_mp1_v13_0.h"
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#define ACA_MARK_FATAL_FLAG 0x100
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#define ACA_MARK_UE_READ_FLAG 0x1
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#define blk_name(block_id) ras_core_get_ras_block_name(block_id)
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static struct aca_regs_dump {
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const char *name;
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int reg_idx;
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} aca_regs[] = {
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{"CONTROL", ACA_REG_IDX__CTL},
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{"STATUS", ACA_REG_IDX__STATUS},
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{"ADDR", ACA_REG_IDX__ADDR},
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{"MISC", ACA_REG_IDX__MISC0},
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{"CONFIG", ACA_REG_IDX__CONFG},
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{"IPID", ACA_REG_IDX__IPID},
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{"SYND", ACA_REG_IDX__SYND},
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{"DESTAT", ACA_REG_IDX__DESTAT},
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{"DEADDR", ACA_REG_IDX__DEADDR},
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{"CONTROL_MASK", ACA_REG_IDX__CTL_MASK},
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};
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static void aca_report_ecc_info(struct ras_core_context *ras_core,
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u64 seq_no, u32 blk, u32 skt, u32 aid,
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struct aca_aid_ecc *aid_ecc,
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struct aca_bank_ecc *new_ecc)
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{
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struct aca_ecc_count ecc_count = {0};
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ecc_count.new_ue_count = new_ecc->ue_count;
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ecc_count.new_de_count = new_ecc->de_count;
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ecc_count.new_ce_count = new_ecc->ce_count;
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if (blk == RAS_BLOCK_ID__GFX) {
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struct aca_ecc_count *xcd_ecc;
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int xcd_id;
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for (xcd_id = 0; xcd_id < aid_ecc->xcd.xcd_num; xcd_id++) {
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xcd_ecc = &aid_ecc->xcd.xcd[xcd_id].ecc_err;
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ecc_count.total_ue_count += xcd_ecc->total_ue_count;
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ecc_count.total_de_count += xcd_ecc->total_de_count;
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ecc_count.total_ce_count += xcd_ecc->total_ce_count;
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}
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} else {
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ecc_count.total_ue_count = aid_ecc->ecc_err.total_ue_count;
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ecc_count.total_de_count = aid_ecc->ecc_err.total_de_count;
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ecc_count.total_ce_count = aid_ecc->ecc_err.total_ce_count;
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}
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if (ecc_count.new_ue_count) {
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RAS_DEV_INFO(ras_core->dev,
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"{%llu} socket: %d, die: %d, %u new uncorrectable hardware errors detected in %s block\n",
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seq_no, skt, aid, ecc_count.new_ue_count, blk_name(blk));
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RAS_DEV_INFO(ras_core->dev,
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"{%llu} socket: %d, die: %d, %u uncorrectable hardware errors detected in total in %s block\n",
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seq_no, skt, aid, ecc_count.total_ue_count, blk_name(blk));
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}
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if (ecc_count.new_de_count) {
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RAS_DEV_INFO(ras_core->dev,
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"{%llu} socket: %d, die: %d, %u new %s detected in %s block\n",
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seq_no, skt, aid, ecc_count.new_de_count,
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(blk == RAS_BLOCK_ID__UMC) ?
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"deferred hardware errors" : "poison consumption",
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blk_name(blk));
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RAS_DEV_INFO(ras_core->dev,
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"{%llu} socket: %d, die: %d, %u %s detected in total in %s block\n",
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seq_no, skt, aid, ecc_count.total_de_count,
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(blk == RAS_BLOCK_ID__UMC) ?
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"deferred hardware errors" : "poison consumption",
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blk_name(blk));
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}
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if (ecc_count.new_ce_count) {
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RAS_DEV_INFO(ras_core->dev,
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"{%llu} socket: %d, die: %d, %u new correctable hardware errors detected in %s block\n",
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seq_no, skt, aid, ecc_count.new_ce_count, blk_name(blk));
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RAS_DEV_INFO(ras_core->dev,
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"{%llu} socket: %d, die: %d, %u correctable hardware errors detected in total in %s block\n",
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seq_no, skt, aid, ecc_count.total_ce_count, blk_name(blk));
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}
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}
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static void aca_bank_log(struct ras_core_context *ras_core,
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int idx, int total, struct aca_bank_reg *bank,
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struct aca_bank_ecc *bank_ecc)
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{
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int i;
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RAS_DEV_INFO(ras_core->dev,
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"{%llu}" RAS_HW_ERR "Accelerator Check Architecture events logged\n",
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bank->seq_no);
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/* plus 1 for output format, e.g: ACA[08/08]: xxxx */
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for (i = 0; i < ARRAY_SIZE(aca_regs); i++)
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RAS_DEV_INFO(ras_core->dev,
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"{%llu}" RAS_HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n",
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bank->seq_no, idx + 1, total,
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aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]);
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}
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static void aca_log_bank_data(struct ras_core_context *ras_core,
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struct aca_bank_reg *bank, struct aca_bank_ecc *bank_ecc,
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struct ras_log_batch_tag *batch)
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{
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if (bank_ecc->ue_count)
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ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_UE, bank->regs, batch);
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else if (bank_ecc->de_count)
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ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_DE, bank->regs, batch);
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else
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ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_CE, bank->regs, batch);
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}
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static int aca_get_bank_count(struct ras_core_context *ras_core,
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enum ras_err_type type, u32 *count)
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{
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return ras_mp1_get_bank_count(ras_core, type, count);
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}
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static bool aca_match_bank(struct aca_block *aca_blk, struct aca_bank_reg *bank)
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{
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const struct aca_bank_hw_ops *bank_ops;
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if (!aca_blk->blk_info)
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return false;
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bank_ops = &aca_blk->blk_info->bank_ops;
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if (!bank_ops->bank_match)
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return false;
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return bank_ops->bank_match(aca_blk, bank);
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}
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static int aca_parse_bank(struct ras_core_context *ras_core,
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struct aca_block *aca_blk,
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struct aca_bank_reg *bank,
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struct aca_bank_ecc *ecc)
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{
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const struct aca_bank_hw_ops *bank_ops = &aca_blk->blk_info->bank_ops;
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if (!bank_ops || !bank_ops->bank_parse)
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return -RAS_CORE_NOT_SUPPORTED;
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return bank_ops->bank_parse(ras_core, aca_blk, bank, ecc);
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}
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static int aca_check_block_ecc_info(struct ras_core_context *ras_core,
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struct aca_block *aca_blk, struct aca_ecc_info *info)
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{
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if (info->socket_id >= aca_blk->ecc.socket_num_per_hive) {
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RAS_DEV_ERR(ras_core->dev,
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"Socket id (%d) is out of config! max:%u\n",
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info->socket_id, aca_blk->ecc.socket_num_per_hive);
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return -ENODATA;
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}
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if (info->die_id >= aca_blk->ecc.socket[info->socket_id].aid_num) {
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RAS_DEV_ERR(ras_core->dev,
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"Die id (%d) is out of config! max:%u\n",
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info->die_id, aca_blk->ecc.socket[info->socket_id].aid_num);
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return -ENODATA;
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}
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if ((aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__GFX) &&
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(info->xcd_id >=
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aca_blk->ecc.socket[info->socket_id].aid[info->die_id].xcd.xcd_num)) {
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RAS_DEV_ERR(ras_core->dev,
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"Xcd id (%d) is out of config! max:%u\n",
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info->xcd_id,
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aca_blk->ecc.socket[info->socket_id].aid[info->die_id].xcd.xcd_num);
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return -ENODATA;
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}
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return 0;
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}
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static int aca_log_bad_bank(struct ras_core_context *ras_core,
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struct aca_block *aca_blk, struct aca_bank_reg *bank,
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struct aca_bank_ecc *bank_ecc)
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{
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struct aca_ecc_info *info;
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struct aca_ecc_count *ecc_err;
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struct aca_aid_ecc *aid_ecc;
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int ret;
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info = &bank_ecc->bank_info;
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ret = aca_check_block_ecc_info(ras_core, aca_blk, info);
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if (ret)
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return ret;
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mutex_lock(&ras_core->ras_aca.aca_lock);
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aid_ecc = &aca_blk->ecc.socket[info->socket_id].aid[info->die_id];
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if (aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__GFX)
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ecc_err = &aid_ecc->xcd.xcd[info->xcd_id].ecc_err;
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else
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ecc_err = &aid_ecc->ecc_err;
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ecc_err->new_ce_count += bank_ecc->ce_count;
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ecc_err->total_ce_count += bank_ecc->ce_count;
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ecc_err->new_ue_count += bank_ecc->ue_count;
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ecc_err->total_ue_count += bank_ecc->ue_count;
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ecc_err->new_de_count += bank_ecc->de_count;
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ecc_err->total_de_count += bank_ecc->de_count;
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mutex_unlock(&ras_core->ras_aca.aca_lock);
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if ((aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__UMC) &&
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bank_ecc->de_count) {
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struct ras_bank_ecc ras_ecc = {0};
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ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core);
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ras_ecc.addr = bank_ecc->bank_info.addr;
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ras_ecc.ipid = bank_ecc->bank_info.ipid;
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ras_ecc.status = bank_ecc->bank_info.status;
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ras_ecc.seq_no = bank->seq_no;
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if (ras_core_gpu_in_reset(ras_core))
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ras_umc_log_bad_bank_pending(ras_core, &ras_ecc);
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else
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ras_umc_log_bad_bank(ras_core, &ras_ecc);
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}
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aca_report_ecc_info(ras_core,
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bank->seq_no, aca_blk->blk_info->ras_block_id, info->socket_id, info->die_id,
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&aca_blk->ecc.socket[info->socket_id].aid[info->die_id], bank_ecc);
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return 0;
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}
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static struct aca_block *aca_get_bank_aca_block(struct ras_core_context *ras_core,
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struct aca_bank_reg *bank)
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{
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int i = 0;
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for (i = 0; i < RAS_BLOCK_ID__LAST; i++)
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if (aca_match_bank(&ras_core->ras_aca.aca_blk[i], bank))
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return &ras_core->ras_aca.aca_blk[i];
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return NULL;
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}
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static int aca_dump_bank(struct ras_core_context *ras_core, u32 ecc_type,
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int idx, void *data)
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{
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struct aca_bank_reg *bank = (struct aca_bank_reg *)data;
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int i, ret, reg_cnt;
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reg_cnt = min_t(int, 16, ARRAY_SIZE(bank->regs));
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for (i = 0; i < reg_cnt; i++) {
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ret = ras_mp1_dump_bank(ras_core, ecc_type, idx, i, &bank->regs[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static uint64_t aca_get_bank_seqno(struct ras_core_context *ras_core,
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enum ras_err_type err_type, struct aca_block *aca_blk,
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struct aca_bank_ecc *bank_ecc)
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{
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uint64_t seq_no = 0;
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if (bank_ecc->de_count) {
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if (aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__UMC)
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seq_no = ras_core_get_seqno(ras_core, RAS_SEQNO_TYPE_DE, true);
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else
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seq_no = ras_core_get_seqno(ras_core,
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RAS_SEQNO_TYPE_POISON_CONSUMPTION, true);
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} else if (bank_ecc->ue_count) {
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seq_no = ras_core_get_seqno(ras_core, RAS_SEQNO_TYPE_UE, true);
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} else {
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seq_no = ras_core_get_seqno(ras_core, RAS_SEQNO_TYPE_CE, true);
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}
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return seq_no;
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}
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static bool aca_dup_update_ue_in_fatal(struct ras_core_context *ras_core,
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u32 ecc_type)
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{
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struct ras_aca *aca = &ras_core->ras_aca;
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if (ecc_type != RAS_ERR_TYPE__UE)
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return false;
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if (aca->ue_updated_mark & ACA_MARK_FATAL_FLAG) {
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if (aca->ue_updated_mark & ACA_MARK_UE_READ_FLAG)
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return true;
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aca->ue_updated_mark |= ACA_MARK_UE_READ_FLAG;
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}
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return false;
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}
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void ras_aca_mark_fatal_flag(struct ras_core_context *ras_core)
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{
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struct ras_aca *aca = &ras_core->ras_aca;
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if (!aca)
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return;
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aca->ue_updated_mark |= ACA_MARK_FATAL_FLAG;
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}
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void ras_aca_clear_fatal_flag(struct ras_core_context *ras_core)
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{
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struct ras_aca *aca = &ras_core->ras_aca;
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if (!aca)
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return;
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if ((aca->ue_updated_mark & ACA_MARK_FATAL_FLAG) &&
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(aca->ue_updated_mark & ACA_MARK_UE_READ_FLAG))
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aca->ue_updated_mark = 0;
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}
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static int aca_banks_update(struct ras_core_context *ras_core,
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u32 ecc_type, void *data)
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{
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struct aca_bank_reg bank;
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struct aca_block *aca_blk;
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struct aca_bank_ecc bank_ecc;
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struct ras_log_batch_tag *batch_tag = NULL;
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u32 count = 0;
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int ret;
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int i;
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mutex_lock(&ras_core->ras_aca.bank_op_lock);
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if (aca_dup_update_ue_in_fatal(ras_core, ecc_type))
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goto out;
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ret = aca_get_bank_count(ras_core, ecc_type, &count);
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if (ret)
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goto out;
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if (!count)
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goto out;
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batch_tag = ras_log_ring_create_batch_tag(ras_core);
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for (i = 0; i < count; i++) {
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memset(&bank, 0, sizeof(bank));
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ret = aca_dump_bank(ras_core, ecc_type, i, &bank);
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if (ret)
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break;
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bank.ecc_type = ecc_type;
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memset(&bank_ecc, 0, sizeof(bank_ecc));
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aca_blk = aca_get_bank_aca_block(ras_core, &bank);
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if (aca_blk)
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ret = aca_parse_bank(ras_core, aca_blk, &bank, &bank_ecc);
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bank.seq_no = aca_get_bank_seqno(ras_core, ecc_type, aca_blk, &bank_ecc);
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aca_log_bank_data(ras_core, &bank, &bank_ecc, batch_tag);
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aca_bank_log(ras_core, i, count, &bank, &bank_ecc);
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if (!ret && aca_blk)
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ret = aca_log_bad_bank(ras_core, aca_blk, &bank, &bank_ecc);
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if (ret)
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break;
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}
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ras_log_ring_destroy_batch_tag(ras_core, batch_tag);
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out:
|
||||
mutex_unlock(&ras_core->ras_aca.bank_op_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ras_aca_update_ecc(struct ras_core_context *ras_core, u32 type, void *data)
|
||||
{
|
||||
/* Update aca bank to aca source error_cache first */
|
||||
return aca_banks_update(ras_core, type, data);
|
||||
}
|
||||
|
||||
static struct aca_block *ras_aca_get_block_handle(struct ras_core_context *ras_core, uint32_t blk)
|
||||
{
|
||||
return &ras_core->ras_aca.aca_blk[blk];
|
||||
}
|
||||
|
||||
static int ras_aca_clear_block_ecc_count(struct ras_core_context *ras_core, u32 blk)
|
||||
{
|
||||
struct aca_block *aca_blk;
|
||||
struct aca_aid_ecc *aid_ecc;
|
||||
int skt, aid, xcd;
|
||||
|
||||
mutex_lock(&ras_core->ras_aca.aca_lock);
|
||||
aca_blk = ras_aca_get_block_handle(ras_core, blk);
|
||||
for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) {
|
||||
for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) {
|
||||
aid_ecc = &aca_blk->ecc.socket[skt].aid[aid];
|
||||
if (blk == RAS_BLOCK_ID__GFX) {
|
||||
for (xcd = 0; xcd < aid_ecc->xcd.xcd_num; xcd++)
|
||||
memset(&aid_ecc->xcd.xcd[xcd],
|
||||
0, sizeof(struct aca_xcd_ecc));
|
||||
} else {
|
||||
memset(&aid_ecc->ecc_err, 0, sizeof(aid_ecc->ecc_err));
|
||||
}
|
||||
}
|
||||
}
|
||||
mutex_unlock(&ras_core->ras_aca.aca_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ras_aca_clear_all_blocks_ecc_count(struct ras_core_context *ras_core)
|
||||
{
|
||||
enum ras_block_id blk;
|
||||
int ret;
|
||||
|
||||
for (blk = RAS_BLOCK_ID__UMC; blk < RAS_BLOCK_ID__LAST; blk++) {
|
||||
ret = ras_aca_clear_block_ecc_count(ras_core, blk);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ras_aca_clear_block_new_ecc_count(struct ras_core_context *ras_core, u32 blk)
|
||||
{
|
||||
struct aca_block *aca_blk;
|
||||
int skt, aid, xcd;
|
||||
struct aca_ecc_count *ecc_err;
|
||||
struct aca_aid_ecc *aid_ecc;
|
||||
|
||||
mutex_lock(&ras_core->ras_aca.aca_lock);
|
||||
aca_blk = ras_aca_get_block_handle(ras_core, blk);
|
||||
for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) {
|
||||
for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) {
|
||||
aid_ecc = &aca_blk->ecc.socket[skt].aid[aid];
|
||||
if (blk == RAS_BLOCK_ID__GFX) {
|
||||
for (xcd = 0; xcd < aid_ecc->xcd.xcd_num; xcd++) {
|
||||
ecc_err = &aid_ecc->xcd.xcd[xcd].ecc_err;
|
||||
ecc_err->new_ce_count = 0;
|
||||
ecc_err->new_ue_count = 0;
|
||||
ecc_err->new_de_count = 0;
|
||||
}
|
||||
} else {
|
||||
ecc_err = &aid_ecc->ecc_err;
|
||||
ecc_err->new_ce_count = 0;
|
||||
ecc_err->new_ue_count = 0;
|
||||
ecc_err->new_de_count = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
mutex_unlock(&ras_core->ras_aca.aca_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ras_aca_get_block_each_aid_ecc_count(struct ras_core_context *ras_core,
|
||||
u32 blk, u32 skt, u32 aid, u32 xcd,
|
||||
struct aca_ecc_count *ecc_count)
|
||||
{
|
||||
struct aca_block *aca_blk;
|
||||
struct aca_ecc_count *ecc_err;
|
||||
|
||||
aca_blk = ras_aca_get_block_handle(ras_core, blk);
|
||||
if (blk == RAS_BLOCK_ID__GFX)
|
||||
ecc_err = &aca_blk->ecc.socket[skt].aid[aid].xcd.xcd[xcd].ecc_err;
|
||||
else
|
||||
ecc_err = &aca_blk->ecc.socket[skt].aid[aid].ecc_err;
|
||||
|
||||
ecc_count->new_ce_count = ecc_err->new_ce_count;
|
||||
ecc_count->total_ce_count = ecc_err->total_ce_count;
|
||||
ecc_count->new_ue_count = ecc_err->new_ue_count;
|
||||
ecc_count->total_ue_count = ecc_err->total_ue_count;
|
||||
ecc_count->new_de_count = ecc_err->new_de_count;
|
||||
ecc_count->total_de_count = ecc_err->total_de_count;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void _add_ecc_count(struct aca_ecc_count *des, struct aca_ecc_count *src)
|
||||
{
|
||||
des->new_ce_count += src->new_ce_count;
|
||||
des->total_ce_count += src->total_ce_count;
|
||||
des->new_ue_count += src->new_ue_count;
|
||||
des->total_ue_count += src->total_ue_count;
|
||||
des->new_de_count += src->new_de_count;
|
||||
des->total_de_count += src->total_de_count;
|
||||
}
|
||||
|
||||
static const struct ras_aca_ip_func *aca_get_ip_func(
|
||||
struct ras_core_context *ras_core, uint32_t ip_version)
|
||||
{
|
||||
switch (ip_version) {
|
||||
case IP_VERSION(1, 0, 0):
|
||||
return &ras_aca_func_v1_0;
|
||||
default:
|
||||
RAS_DEV_ERR(ras_core->dev,
|
||||
"ACA ip version(0x%x) is not supported!\n", ip_version);
|
||||
break;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int ras_aca_get_block_ecc_count(struct ras_core_context *ras_core,
|
||||
u32 blk, void *data)
|
||||
{
|
||||
struct ras_ecc_count *err_data = (struct ras_ecc_count *)data;
|
||||
struct aca_block *aca_blk;
|
||||
int skt, aid, xcd;
|
||||
struct aca_ecc_count ecc_xcd;
|
||||
struct aca_ecc_count ecc_aid;
|
||||
struct aca_ecc_count ecc;
|
||||
|
||||
if (blk >= RAS_BLOCK_ID__LAST)
|
||||
return -EINVAL;
|
||||
|
||||
if (!err_data)
|
||||
return -EINVAL;
|
||||
|
||||
aca_blk = ras_aca_get_block_handle(ras_core, blk);
|
||||
memset(&ecc, 0, sizeof(ecc));
|
||||
|
||||
mutex_lock(&ras_core->ras_aca.aca_lock);
|
||||
if (blk == RAS_BLOCK_ID__GFX) {
|
||||
for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) {
|
||||
for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) {
|
||||
memset(&ecc_aid, 0, sizeof(ecc_aid));
|
||||
for (xcd = 0;
|
||||
xcd < aca_blk->ecc.socket[skt].aid[aid].xcd.xcd_num;
|
||||
xcd++) {
|
||||
memset(&ecc_xcd, 0, sizeof(ecc_xcd));
|
||||
if (ras_aca_get_block_each_aid_ecc_count(ras_core,
|
||||
blk, skt, aid, xcd, &ecc_xcd))
|
||||
continue;
|
||||
_add_ecc_count(&ecc_aid, &ecc_xcd);
|
||||
}
|
||||
_add_ecc_count(&ecc, &ecc_aid);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) {
|
||||
for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) {
|
||||
memset(&ecc_aid, 0, sizeof(ecc_aid));
|
||||
if (ras_aca_get_block_each_aid_ecc_count(ras_core,
|
||||
blk, skt, aid, 0, &ecc_aid))
|
||||
continue;
|
||||
_add_ecc_count(&ecc, &ecc_aid);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
err_data->new_ce_count = ecc.new_ce_count;
|
||||
err_data->total_ce_count = ecc.total_ce_count;
|
||||
err_data->new_ue_count = ecc.new_ue_count;
|
||||
err_data->total_ue_count = ecc.total_ue_count;
|
||||
err_data->new_de_count = ecc.new_de_count;
|
||||
err_data->total_de_count = ecc.total_de_count;
|
||||
mutex_unlock(&ras_core->ras_aca.aca_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ras_aca_sw_init(struct ras_core_context *ras_core)
|
||||
{
|
||||
struct ras_aca *ras_aca = &ras_core->ras_aca;
|
||||
struct ras_aca_config *aca_cfg = &ras_core->config->aca_cfg;
|
||||
struct aca_block *aca_blk;
|
||||
uint32_t socket_num_per_hive;
|
||||
uint32_t aid_num_per_socket;
|
||||
uint32_t xcd_num_per_aid;
|
||||
int blk, skt, aid;
|
||||
|
||||
socket_num_per_hive = aca_cfg->socket_num_per_hive;
|
||||
aid_num_per_socket = aca_cfg->aid_num_per_socket;
|
||||
xcd_num_per_aid = aca_cfg->xcd_num_per_aid;
|
||||
|
||||
if (!xcd_num_per_aid || !aid_num_per_socket ||
|
||||
(socket_num_per_hive > MAX_SOCKET_NUM_PER_HIVE) ||
|
||||
(aid_num_per_socket > MAX_AID_NUM_PER_SOCKET) ||
|
||||
(xcd_num_per_aid > MAX_XCD_NUM_PER_AID)) {
|
||||
RAS_DEV_ERR(ras_core->dev, "Invalid ACA system configuration: %d, %d, %d\n",
|
||||
socket_num_per_hive, aid_num_per_socket, xcd_num_per_aid);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
memset(ras_aca, 0, sizeof(*ras_aca));
|
||||
|
||||
for (blk = 0; blk < RAS_BLOCK_ID__LAST; blk++) {
|
||||
aca_blk = &ras_aca->aca_blk[blk];
|
||||
aca_blk->ecc.socket_num_per_hive = socket_num_per_hive;
|
||||
for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) {
|
||||
aca_blk->ecc.socket[skt].aid_num = aid_num_per_socket;
|
||||
if (blk == RAS_BLOCK_ID__GFX) {
|
||||
for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++)
|
||||
aca_blk->ecc.socket[skt].aid[aid].xcd.xcd_num =
|
||||
xcd_num_per_aid;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mutex_init(&ras_aca->aca_lock);
|
||||
mutex_init(&ras_aca->bank_op_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ras_aca_sw_fini(struct ras_core_context *ras_core)
|
||||
{
|
||||
struct ras_aca *ras_aca = &ras_core->ras_aca;
|
||||
|
||||
mutex_destroy(&ras_aca->aca_lock);
|
||||
mutex_destroy(&ras_aca->bank_op_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ras_aca_hw_init(struct ras_core_context *ras_core)
|
||||
{
|
||||
struct ras_aca *ras_aca = &ras_core->ras_aca;
|
||||
struct aca_block *aca_blk;
|
||||
const struct ras_aca_ip_func *ip_func;
|
||||
int i;
|
||||
|
||||
ras_aca->aca_ip_version = ras_core->config->aca_ip_version;
|
||||
ip_func = aca_get_ip_func(ras_core, ras_aca->aca_ip_version);
|
||||
if (!ip_func)
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < ip_func->block_num; i++) {
|
||||
aca_blk = &ras_aca->aca_blk[ip_func->block_info[i]->ras_block_id];
|
||||
aca_blk->blk_info = ip_func->block_info[i];
|
||||
}
|
||||
|
||||
ras_aca->ue_updated_mark = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ras_aca_hw_fini(struct ras_core_context *ras_core)
|
||||
{
|
||||
struct ras_aca *ras_aca = &ras_core->ras_aca;
|
||||
|
||||
ras_aca->ue_updated_mark = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
164
drivers/gpu/drm/amd/ras/rascore/ras_aca.h
Normal file
164
drivers/gpu/drm/amd/ras/rascore/ras_aca.h
Normal file
|
|
@ -0,0 +1,164 @@
|
|||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright 2025 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __RAS_ACA_H__
|
||||
#define __RAS_ACA_H__
|
||||
#include "ras.h"
|
||||
|
||||
#define MAX_SOCKET_NUM_PER_HIVE 8
|
||||
#define MAX_AID_NUM_PER_SOCKET 4
|
||||
#define MAX_XCD_NUM_PER_AID 2
|
||||
#define MAX_ACA_RAS_BLOCK 20
|
||||
|
||||
#define ACA_ERROR__UE_MASK (0x1 << RAS_ERR_TYPE__UE)
|
||||
#define ACA_ERROR__CE_MASK (0x1 << RAS_ERR_TYPE__CE)
|
||||
#define ACA_ERROR__DE_MASK (0x1 << RAS_ERR_TYPE__DE)
|
||||
|
||||
enum ras_aca_reg_idx {
|
||||
ACA_REG_IDX__CTL = 0,
|
||||
ACA_REG_IDX__STATUS = 1,
|
||||
ACA_REG_IDX__ADDR = 2,
|
||||
ACA_REG_IDX__MISC0 = 3,
|
||||
ACA_REG_IDX__CONFG = 4,
|
||||
ACA_REG_IDX__IPID = 5,
|
||||
ACA_REG_IDX__SYND = 6,
|
||||
ACA_REG_IDX__DESTAT = 8,
|
||||
ACA_REG_IDX__DEADDR = 9,
|
||||
ACA_REG_IDX__CTL_MASK = 10,
|
||||
ACA_REG_MAX_COUNT = 16,
|
||||
};
|
||||
|
||||
struct ras_core_context;
|
||||
struct aca_block;
|
||||
|
||||
struct aca_bank_reg {
|
||||
u32 ecc_type;
|
||||
u64 seq_no;
|
||||
u64 regs[ACA_REG_MAX_COUNT];
|
||||
};
|
||||
|
||||
enum aca_ecc_hwip {
|
||||
ACA_ECC_HWIP__UNKNOWN = -1,
|
||||
ACA_ECC_HWIP__PSP = 0,
|
||||
ACA_ECC_HWIP__UMC,
|
||||
ACA_ECC_HWIP__SMU,
|
||||
ACA_ECC_HWIP__PCS_XGMI,
|
||||
ACA_ECC_HWIP_COUNT,
|
||||
};
|
||||
|
||||
struct aca_ecc_info {
|
||||
int die_id;
|
||||
int socket_id;
|
||||
int xcd_id;
|
||||
int hwid;
|
||||
int mcatype;
|
||||
uint64_t status;
|
||||
uint64_t ipid;
|
||||
uint64_t addr;
|
||||
};
|
||||
|
||||
struct aca_bank_ecc {
|
||||
struct aca_ecc_info bank_info;
|
||||
u32 ce_count;
|
||||
u32 ue_count;
|
||||
u32 de_count;
|
||||
};
|
||||
|
||||
struct aca_ecc_count {
|
||||
u32 new_ce_count;
|
||||
u32 total_ce_count;
|
||||
u32 new_ue_count;
|
||||
u32 total_ue_count;
|
||||
u32 new_de_count;
|
||||
u32 total_de_count;
|
||||
};
|
||||
|
||||
struct aca_xcd_ecc {
|
||||
struct aca_ecc_count ecc_err;
|
||||
};
|
||||
|
||||
struct aca_aid_ecc {
|
||||
union {
|
||||
struct aca_xcd {
|
||||
struct aca_xcd_ecc xcd[MAX_XCD_NUM_PER_AID];
|
||||
u32 xcd_num;
|
||||
} xcd;
|
||||
struct aca_ecc_count ecc_err;
|
||||
};
|
||||
};
|
||||
|
||||
struct aca_socket_ecc {
|
||||
struct aca_aid_ecc aid[MAX_AID_NUM_PER_SOCKET];
|
||||
u32 aid_num;
|
||||
};
|
||||
|
||||
struct aca_block_ecc {
|
||||
struct aca_socket_ecc socket[MAX_SOCKET_NUM_PER_HIVE];
|
||||
u32 socket_num_per_hive;
|
||||
};
|
||||
|
||||
struct aca_bank_hw_ops {
|
||||
bool (*bank_match)(struct aca_block *ras_blk, void *data);
|
||||
int (*bank_parse)(struct ras_core_context *ras_core,
|
||||
struct aca_block *aca_blk, void *data, void *buf);
|
||||
};
|
||||
|
||||
struct aca_block_info {
|
||||
char name[32];
|
||||
u32 ras_block_id;
|
||||
enum aca_ecc_hwip hwip;
|
||||
struct aca_bank_hw_ops bank_ops;
|
||||
u32 mask;
|
||||
};
|
||||
|
||||
struct aca_block {
|
||||
const struct aca_block_info *blk_info;
|
||||
struct aca_block_ecc ecc;
|
||||
};
|
||||
|
||||
struct ras_aca_ip_func {
|
||||
uint32_t block_num;
|
||||
const struct aca_block_info **block_info;
|
||||
};
|
||||
|
||||
struct ras_aca {
|
||||
uint32_t aca_ip_version;
|
||||
const struct ras_aca_ip_func *ip_func;
|
||||
struct mutex aca_lock;
|
||||
struct mutex bank_op_lock;
|
||||
struct aca_block aca_blk[MAX_ACA_RAS_BLOCK];
|
||||
uint32_t ue_updated_mark;
|
||||
};
|
||||
|
||||
int ras_aca_sw_init(struct ras_core_context *ras_core);
|
||||
int ras_aca_sw_fini(struct ras_core_context *ras_core);
|
||||
int ras_aca_hw_init(struct ras_core_context *ras_core);
|
||||
int ras_aca_hw_fini(struct ras_core_context *ras_core);
|
||||
int ras_aca_get_block_ecc_count(struct ras_core_context *ras_core, u32 blk, void *data);
|
||||
int ras_aca_clear_block_new_ecc_count(struct ras_core_context *ras_core, u32 blk);
|
||||
int ras_aca_clear_all_blocks_ecc_count(struct ras_core_context *ras_core);
|
||||
int ras_aca_update_ecc(struct ras_core_context *ras_core, u32 ecc_type, void *data);
|
||||
void ras_aca_mark_fatal_flag(struct ras_core_context *ras_core);
|
||||
void ras_aca_clear_fatal_flag(struct ras_core_context *ras_core);
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user