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clk: qcom: cmnpll: Account for reference clock divider

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The clk_cmn_pll_recalc_rate() function must account for the reference clock
divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
with a reference divider other than 1 calculate incorrect CMN PLL rates.
For example, on IPQ5332 where the reference divider is 2, the computed rate
becomes twice the actual output.

Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
applying the 2 * FACTOR scaling. This yields the correct rate calculation:
rate = (parent_rate / ref_div) * 2 * factor.

Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
IPQ5424, IPQ5018) that use ref_div = 1.

Fixes: f81715a4c8 ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC")
Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-1-f9f7e4efbd79@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Luo Jie 2026-01-06 21:35:10 -08:00 committed by Bjorn Andersson
parent 0e5f38b892
commit 88c543fff7
1 changed files with 9 additions and 2 deletions
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11
drivers/clk/qcom/ipq-cmn-pll.c
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@ -199,7 +199,7 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate) unsigned long parent_rate)
{ {
struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw); struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
u32 val, factor; u32 val, factor, ref_div;
/* /*
* The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted
@ -207,8 +207,15 @@ static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
*/ */
regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);
factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val); factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val);
if (WARN_ON(factor == 0))
factor = 1;
return parent_rate * 2 * factor; regmap_read(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, &val);
ref_div = FIELD_GET(CMN_PLL_REFCLK_DIV, val);
if (WARN_ON(ref_div == 0))
ref_div = 1;
return div_u64((u64)parent_rate * 2 * factor, ref_div);
} }
static int clk_cmn_pll_determine_rate(struct clk_hw *hw, static int clk_cmn_pll_determine_rate(struct clk_hw *hw,