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arm64: dts: ti: Add support for Variscite VAR-SOM-AM62
Add device tree support for the Variscite VAR-SOM-AM62 system on module. This SOM is designed to be used with various carrier boards. The module includes: - AM62x Sitara MPU processor - Up to 4GB of DDR4-3733 memory - Up to 128GB eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices - Audio codec wm8904 - Resistive touch panel interface controller - I2C, UART and SPI interfaces - Bluetooth 5.2 + WiFi single or dual band Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-som-am62/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Link: https://patch.msgid.link/0a7bdfda80309eaa207b5b369d72f4bcb16e0604.1783864932.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Stefano Radaelli
Vignesh Raghavendra
parent
ff8398281a
commit
887d9e03c4
483
arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi
Normal file
483
arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi
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@ -0,0 +1,483 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Common dtsi for Variscite VAR-SOM-AM62
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*
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* Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-som-am62/
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*
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* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
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* Copyright (C) 2026 Stefano Radaelli <stefano.r@variscite.com>
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*
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "k3-am625.dtsi"
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/ {
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compatible = "variscite,var-som-am62", "ti,am625";
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memory@80000000 {
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/* 2G RAM */
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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device_type = "memory";
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bootph-pre-ram;
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};
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mmc_pwrseq: mmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mmc_pwrseq>;
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reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
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};
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opp-table {
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/* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */
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opp-1400000000 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-supported-hw = <0x01 0x0004>;
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clock-latency-ns = <6000000>;
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};
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ramoops@9ca00000 {
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compatible = "ramoops";
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reg = <0x00 0x9ca00000 0x00 0x00100000>;
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record-size = <0x8000>;
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console-size = <0x8000>;
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ftrace-size = <0x00>;
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pmsg-size = <0x8000>;
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};
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/* global cma region */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x00 0x8000000>;
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linux,cma-default;
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};
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rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0x9b500000 0x00 0x00300000>;
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no-map;
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};
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wkup_r5fss0_core0_dma_memory_region: memory@9da00000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0x9da00000 0x00 0x100000>;
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no-map;
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};
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wkup_r5fss0_core0_memory_region: memory@9db00000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0x9db00000 0x00 0xc00000>;
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no-map;
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};
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secure_tfa_ddr: tfa@9e780000 {
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reg = <0x00 0x9e780000 0x00 0x80000>;
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alignment = <0x1000>;
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no-map;
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};
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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};
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reg_1v8: regulator-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "On-module +V1.8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <®_3v3>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "On-module +V3.3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_3v3_phy: regulator-3v3-phy {
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compatible = "regulator-fixed";
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regulator-name = "On-module +V3.3_PHY";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eth_phy>;
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gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,bitclock-master = <&codec_dai>;
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simple-audio-card,format = "dsp_b";
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simple-audio-card,frame-master = <&codec_dai>;
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simple-audio-card,name = "wm8904-audio";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,routing =
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"Headphone Jack", "HPOUTL",
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"Headphone Jack", "HPOUTR",
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"IN2L", "Line In Jack",
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"IN2R", "Line In Jack",
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"IN1L", "Microphone Jack",
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"IN1R", "Microphone Jack";
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simple-audio-card,widgets =
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"Microphone", "Microphone Jack",
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"Headphone", "Headphone Jack",
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"Line", "Line In Jack";
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codec_dai: simple-audio-card,codec {
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sound-dai = <&wm8904>;
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};
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simple-audio-card,cpu {
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sound-dai = <&mcasp1>;
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};
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};
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};
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&audio_refclk1 {
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assigned-clock-rates = <12000000>;
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};
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&cpsw3g {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii1>;
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status = "okay";
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};
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&cpsw3g_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio1>;
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status = "okay";
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cpsw3g_phy0: ethernet-phy@4 {
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compatible = "ethernet-phy-id0283.bc30";
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reg = <4>;
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bootph-all;
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reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <20000>;
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};
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};
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&cpsw_port1 {
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/*
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* The required RGMII TX and RX 2ns delays are implemented directly
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* in hardware via passive delay elements on the SOM PCB.
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* No delay configuration is needed in software via PHY driver.
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*/
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phy-mode = "rgmii";
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phy-handle = <&cpsw3g_phy0>;
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status = "okay";
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};
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&main_i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clock-frequency = <400000>;
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status = "okay";
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wm8904: audio-codec@1a {
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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#sound-dai-cells = <0>;
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clocks = <&audio_refclk1>;
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clock-names = "mclk";
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AVDD-supply = <®_1v8>;
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CPVDD-supply = <®_1v8>;
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DBVDD-supply = <®_3v3>;
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DCVDD-supply = <®_1v8>;
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MICVDD-supply = <®_1v8>;
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wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
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"soft", "music";
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/*
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* Config registers per name, respectively:
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* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
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* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
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* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
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* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
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* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
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*/
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wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
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/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
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/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
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/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
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/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
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/* GPIO1 = DMIC_CLK, don't touch others */
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wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
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};
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};
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&main_i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clock-frequency = <400000>;
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status = "okay";
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};
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&main_pmx0 {
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pinctrl_i2c2: main-i2c2-default-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
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AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
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>;
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};
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pinctrl_i2c3: main-i2c3-default-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */
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AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */
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>;
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};
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pinctrl_mcasp1: main-mcasp1-default-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */
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AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */
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AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */
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AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */
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AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
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>;
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};
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pinctrl_mdio1: main-mdio1-default-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x160, PIN_INPUT, 0) /* (AD24) MDIO0_MDC */
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AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
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>;
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};
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pinctrl_mmc_pwrseq: pinmux-mmc-pwrseq-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (Y25) VOUT0_DATA4.GPIO0_49 */
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>;
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};
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pinctrl_mmc0: main-mmc0-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
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AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
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AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
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AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
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AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
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AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
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AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
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AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
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AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
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AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
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>;
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};
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pinctrl_mmc2: main-mmc2-default-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x120, PIN_INPUT_PULLUP, 0) /* (C24) MMC2_CMD */
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AM62X_IOPAD(0x118, PIN_INPUT_PULLDOWN, 0) /* (D25) MMC2_CLK */
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AM62X_IOPAD(0x114, PIN_INPUT_PULLUP, 0) /* (B24) MMC2_DAT0 */
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AM62X_IOPAD(0x110, PIN_INPUT_PULLUP, 0) /* (C25) MMC2_DAT1 */
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AM62X_IOPAD(0x10c, PIN_INPUT_PULLUP, 0) /* (E23) MMC2_DAT2 */
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AM62X_IOPAD(0x108, PIN_INPUT_PULLUP, 0) /* (D24) MMC2_DAT3 */
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AM62X_IOPAD(0x11c, PIN_INPUT_PULLUP, 0) /* (#N/A) MMC2_CLKB */
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>;
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};
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pinctrl_restouch: main-restouch-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (W24) VOUT0_DATA3.GPIO0_48 */
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>;
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};
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pinctrl_rgmii1: main-rgmii1-default-pins {
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bootph-all;
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pinctrl-single,pins = <
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AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
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AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
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AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
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AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
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AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
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AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
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AM62X_IOPAD(0x134, PIN_INPUT, 0) /* (AE20) RGMII1_TD0 */
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AM62X_IOPAD(0x138, PIN_INPUT, 0) /* (AD20) RGMII1_TD1 */
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AM62X_IOPAD(0x13c, PIN_INPUT, 0) /* (AE18) RGMII1_TD2 */
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AM62X_IOPAD(0x140, PIN_INPUT, 0) /* (AD18) RGMII1_TD3 */
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AM62X_IOPAD(0x130, PIN_INPUT, 0) /* (AE19) RGMII1_TXC */
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AM62X_IOPAD(0x12c, PIN_INPUT, 0) /* (AD19) RGMII1_TX_CTL */
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AM62X_IOPAD(0x00bc, PIN_INPUT, 7) /* (V24) VOUT0_DATA1.GPIO0_46 */
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>;
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};
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pinctrl_eth_phy: main-eth-phy-default-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x00b8, PIN_INPUT, 7) /* (U22) VOUT0_DATA0.GPIO0_45 */
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>;
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};
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pinctrl_spi0: main-spi0-default-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */
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AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */
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AM62X_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B13) SPI0_D0 */
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AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */
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>;
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};
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pinctrl_uart5: main-uart5-default-pins {
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pinctrl-single,pins = <
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AM62X_IOPAD(0x00ec, PIN_INPUT, 4) /* (AA24) VOUT0_DATA13.UART5_CTSn */
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AM62X_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AB25) VOUT0_DATA12.UART5_RTSn */
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AM62X_IOPAD(0x00d0, PIN_INPUT, 4) /* (Y23) VOUT0_DATA6.UART5_RXD */
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AM62X_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AA25) VOUT0_DATA7.UART5_TXD */
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>;
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};
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};
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&mcu_pmx0 {
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pinctrl_wkup_clkout0: wkup-clkout0-default-pins {
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pinctrl-single,pins = <
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AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
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>;
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};
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};
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&main_spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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ti,pindir-d0-out-d1-in;
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status = "okay";
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/* Resistive touch controller */
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ads7846: touchscreen@0 {
|
||||
compatible = "ti,ads7846";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_restouch>;
|
||||
interrupt-parent = <&main_gpio0>;
|
||||
interrupts = <48 IRQ_TYPE_EDGE_FALLING>;
|
||||
spi-max-frequency = <1500000>;
|
||||
pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>;
|
||||
ti,x-min = /bits/ 16 <125>;
|
||||
ti,x-max = /bits/ 16 <4008>;
|
||||
ti,y-min = /bits/ 16 <282>;
|
||||
ti,y-max = /bits/ 16 <3864>;
|
||||
ti,x-plate-ohms = /bits/ 16 <180>;
|
||||
ti,pressure-max = /bits/ 16 <255>;
|
||||
ti,debounce-max = /bits/ 16 <10>;
|
||||
ti,debounce-tol = /bits/ 16 <3>;
|
||||
ti,debounce-rep = /bits/ 16 <1>;
|
||||
ti,settle-delay-usec = /bits/ 16 <150>;
|
||||
ti,keep-vref-on;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
/* On-module Bluetooth */
|
||||
&main_uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mcasp1>;
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
1 0 2 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tdm-slots = <2>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* On-module eMMC */
|
||||
&sdhci0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0>;
|
||||
bootph-all;
|
||||
disable-wp;
|
||||
mmc-pwrseq = <&mmc_pwrseq>;
|
||||
non-removable;
|
||||
status="okay";
|
||||
};
|
||||
|
||||
/* On-module Wi-Fi */
|
||||
&sdhci2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wkup_clkout0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
assigned-clocks = <&k3_clks 157 158>; /* wkup_clkout_sel_out0 */
|
||||
assigned-clock-parents = <&k3_clks 157 164>; /* clk_32k_rc_sel_out0 */
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
cap-power-off-card;
|
||||
status = "okay";
|
||||
|
||||
brcmf: wifi@1 {
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
|
||||
&mcu_gpio0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_gpio_intr {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&wkup_rtc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&wkup_rti0 {
|
||||
/* WKUP RTI0 is used by DM firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
/* WKUP UART0 is used by DM firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_uart1 {
|
||||
/* Main UART1 is used by TIFS firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
#include "k3-am62-ti-ipc-firmware.dtsi"
|
||||
Loading…
Reference in New Issue
Block a user