From da69aeac10c040d78c5bd7e0ee0be0a83f12e856 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 29 Oct 2025 10:39:25 -0500 Subject: [PATCH 1/3] arm64/arm: dts: marvell: Rename "nand-rb" pinctrl node names Update the "nand-rb" pinctrl child node names to use the defined "-pins" suffix fixing DT schema warnings. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-38x.dtsi | 2 +- arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 2 +- arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/marvell/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi index 1181b13deabc..1d616edda322 100644 --- a/arch/arm/boot/dts/marvell/armada-38x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-38x.dtsi @@ -247,7 +247,7 @@ nand_pins: nand-pins { marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp41"; marvell,function = "nand"; }; diff --git a/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi index 7a7e2066c498..a9a71326aafc 100644 --- a/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/marvell/armada-xp-98dx3236.dtsi @@ -322,7 +322,7 @@ nand_pins: nand-pins { marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp19"; marvell,function = "nand"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index 293403a1a333..df939426d258 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -56,7 +56,7 @@ nand_pins: nand-pins { marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp13"; marvell,function = "nf"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi index ee67c70bf02e..fb361d657a77 100644 --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi @@ -89,7 +89,7 @@ nand_pins: nand-pins { marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp13", "mpp12"; marvell,function = "nf"; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 50e9e0724828..3cc320f569ad 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -379,7 +379,7 @@ nand_pins: nand-pins { "mpp27"; marvell,function = "dev"; }; - nand_rb: nand-rb { + nand_rb: nand-rb-pins { marvell,pins = "mpp13"; marvell,function = "nf"; }; From c9b6a836704753fd6fb7e47f5f07c83b408e51d4 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 30 Oct 2025 16:16:25 +0100 Subject: [PATCH 2/3] Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports" This reverts commit 794a066688038df46c01e177cc6faebded0acba4 because it misunderstood interworking between arm trusted firmware and the common phy driver, and does not consistently resolve the issue it was intended to address. Further diagnostics have revealed the root cause for the reported system lock-up in a race condition between pci driver probe and clock core disabling unused clocks. Revert the wrong change restoring driver control over all pci lanes. As a temporary workaround for the original issue, users can boot with "clk_ignore_unused". Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9132-clearfog.dts | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts index 5cf83d8ca1f5..2507896d58f9 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts +++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts @@ -413,13 +413,7 @@ fixed-link { /* SRDS #0,#1,#2,#3 - PCIe */ &cp0_pcie0 { num-lanes = <4>; - /* - * The mvebu-comphy driver does not currently know how to pass correct - * lane-count to ATF while configuring the serdes lanes. - * Rely on bootloader configuration only. - * - * phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; - */ + phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>; status = "okay"; }; @@ -481,13 +475,7 @@ &cp1_eth0 { /* SRDS #0,#1 - PCIe */ &cp1_pcie0 { num-lanes = <2>; - /* - * The mvebu-comphy driver does not currently know how to pass correct - * lane-count to ATF while configuring the serdes lanes. - * Rely on bootloader configuration only. - * - * phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; - */ + phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; status = "okay"; }; From f0e6bc0c3ef4b4afb299bd6912586cafd5d864e9 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 30 Oct 2025 16:16:26 +0100 Subject: [PATCH 3/3] clk: mvebu: cp110 add CLK_IGNORE_UNUSED to pcie_x10, pcie_x11 & pcie_x4 CP110 based platforms rely on the bootloader for pci port initialization. TF-A actively prevents non-uboot re-configuration of pci lanes, and many boards do not have software control over the pci card reset. If a pci port had link at boot-time and the clock is stopped at a later point, the link fails and can not be recovered. PCI controller driver probe - and by extension ownership of a driver for the pci clocks - may be delayed especially on large modular kernels, causing the clock core to start disabling unused clocks. Add the CLK_IGNORE_UNUSED flag to the three pci port's clocks to ensure they are not stopped before the pci controller driver has taken ownership and tested for an existing link. This fixes failed pci link detection when controller driver probes late, e.g. with arm64 defconfig and CONFIG_PHY_MVEBU_CP110_COMPHY=m. Closes: https://lore.kernel.org/r/b71596c7-461b-44b6-89ab-3cfbd492639f@solid-run.com Signed-off-by: Josua Mayer Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- drivers/clk/mvebu/cp110-system-controller.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c index 03c59bf22106..b47c86906046 100644 --- a/drivers/clk/mvebu/cp110-system-controller.c +++ b/drivers/clk/mvebu/cp110-system-controller.c @@ -110,6 +110,25 @@ static const char * const gate_base_names[] = { [CP110_GATE_EIP197] = "eip197" }; +static unsigned long gate_flags(const u8 bit_idx) +{ + switch (bit_idx) { + case CP110_GATE_PCIE_X1_0: + case CP110_GATE_PCIE_X1_1: + case CP110_GATE_PCIE_X4: + /* + * If a port had an active link at boot time, stopping + * the clock creates a failed state from which controller + * driver can not recover. + * Prevent stopping this clock till after a driver has taken + * ownership. + */ + return CLK_IGNORE_UNUSED; + default: + return 0; + } +}; + struct cp110_gate_clk { struct clk_hw hw; struct regmap *regmap; @@ -171,6 +190,7 @@ static struct clk_hw *cp110_register_gate(const char *name, init.ops = &cp110_gate_ops; init.parent_names = &parent_name; init.num_parents = 1; + init.flags = gate_flags(bit_idx); gate->regmap = regmap; gate->bit_idx = bit_idx;