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dmaengine: xilinx_dma: Optimize control register write and channel start logic for AXIDMA and MCDMA in corresponding start_transfer()
Optimize AXI DMA control register programming by consolidating coalesce count and delay configuration into a single register write. Previously, the coalesce count was written separately from the delay configuration, resulting in two register writes. Combine these into one write operation to reduce bus overhead. Additionally, avoid redundant channel starts in xilinx_dma_start_transfer() and xilinx_mcdma_start_transfer() by only calling xilinx_dma_start() when the channel is actually idle. Tested-by: Folker Schwesinger <dev@folker-schwesinger.de> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com> Co-developed-by: Srinivas Neeli <srinivas.neeli@amd.com> Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://patch.msgid.link/20260626092656.1563871-4-suraj.gupta2@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -1603,7 +1603,6 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
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reg &= ~XILINX_DMA_CR_COALESCE_MAX;
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reg |= chan->desc_pendingcount <<
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XILINX_DMA_CR_COALESCE_SHIFT;
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dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
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}
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if (chan->has_sg && list_empty(&chan->active_list))
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@ -1614,7 +1613,8 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
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reg |= XILINX_DMA_DMAXR_ALL_IRQ_MASK;
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dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
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xilinx_dma_start(chan);
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if (chan->idle)
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xilinx_dma_start(chan);
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if (chan->err)
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return;
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@ -1703,7 +1703,8 @@ static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan)
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reg |= XILINX_MCDMA_CR_RUNSTOP_MASK;
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dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg);
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xilinx_dma_start(chan);
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if (chan->idle)
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xilinx_dma_start(chan);
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if (chan->err)
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return;
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