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PM / devfreq: rockchip_dmc: add support for px30
Change-Id: I225088ce179f9b9cd62fce256b87bccb591fd2b2 Signed-off-by: YouMin Chen <cym@rock-chips.com>
This commit is contained in:
YouMin Chen
Tao Huang
parent
326d6f59d1
commit
8865f61ad2
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@ -2,6 +2,7 @@
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Required properties:
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- compatible: Should be one of the following.
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- "rockchip,px30-dmc" - for PX30 SoCs.
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- "rockchip,rk3128-dmc" - for RK3128 SoCs.
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- "rockchip,rk3228-dmc" - for RK3228 SoCs.
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- "rockchip,rk3288-dmc" - for RK3288 SoCs.
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@ -100,6 +100,158 @@ struct share_params {
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static struct share_params *ddr_psci_param;
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/* hope this define can adapt all future platfor */
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static const char * const px30_dts_timing[] = {
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"ddr2_speed_bin",
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"ddr3_speed_bin",
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"ddr4_speed_bin",
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"pd_idle",
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"sr_idle",
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"sr_mc_gate_idle",
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"srpd_lite_idle",
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"standby_idle",
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"auto_pd_dis_freq",
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"auto_sr_dis_freq",
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"ddr2_dll_dis_freq",
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"ddr3_dll_dis_freq",
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"ddr4_dll_dis_freq",
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"phy_dll_dis_freq",
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"ddr2_odt_dis_freq",
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"phy_ddr2_odt_dis_freq",
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"ddr2_drv",
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"ddr2_odt",
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"phy_ddr2_ca_drv",
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"phy_ddr2_ck_drv",
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"phy_ddr2_dq_drv",
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"phy_ddr2_odt",
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"ddr3_odt_dis_freq",
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"phy_ddr3_odt_dis_freq",
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"ddr3_drv",
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"ddr3_odt",
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"phy_ddr3_ca_drv",
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"phy_ddr3_ck_drv",
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"phy_ddr3_dq_drv",
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"phy_ddr3_odt",
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"phy_lpddr2_odt_dis_freq",
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"lpddr2_drv",
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"phy_lpddr2_ca_drv",
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"phy_lpddr2_ck_drv",
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"phy_lpddr2_dq_drv",
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"phy_lpddr2_odt",
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"lpddr3_odt_dis_freq",
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"phy_lpddr3_odt_dis_freq",
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"lpddr3_drv",
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"lpddr3_odt",
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"phy_lpddr3_ca_drv",
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"phy_lpddr3_ck_drv",
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"phy_lpddr3_dq_drv",
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"phy_lpddr3_odt",
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"lpddr4_odt_dis_freq",
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"phy_lpddr4_odt_dis_freq",
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"lpddr4_drv",
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"lpddr4_dq_odt",
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"lpddr4_ca_odt",
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"phy_lpddr4_ca_drv",
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"phy_lpddr4_ck_cs_drv",
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"phy_lpddr4_dq_drv",
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"phy_lpddr4_odt",
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"ddr4_odt_dis_freq",
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"phy_ddr4_odt_dis_freq",
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"ddr4_drv",
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"ddr4_odt",
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"phy_ddr4_ca_drv",
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"phy_ddr4_ck_drv",
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"phy_ddr4_dq_drv",
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"phy_ddr4_odt",
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};
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struct px30_ddr_dts_config_timing {
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unsigned int ddr2_speed_bin;
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unsigned int ddr3_speed_bin;
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unsigned int ddr4_speed_bin;
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unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int auto_sr_dis_freq;
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/* for ddr2 only */
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unsigned int ddr2_dll_dis_freq;
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/* for ddr3 only */
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unsigned int ddr3_dll_dis_freq;
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/* for ddr4 only */
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unsigned int ddr4_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr2_odt_dis_freq;
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unsigned int phy_ddr2_odt_dis_freq;
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unsigned int ddr2_drv;
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unsigned int ddr2_odt;
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unsigned int phy_ddr2_ca_drv;
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unsigned int phy_ddr2_ck_drv;
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unsigned int phy_ddr2_dq_drv;
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unsigned int phy_ddr2_odt;
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unsigned int ddr3_odt_dis_freq;
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unsigned int phy_ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_ck_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int phy_lpddr2_odt_dis_freq;
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unsigned int lpddr2_drv;
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unsigned int phy_lpddr2_ca_drv;
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unsigned int phy_lpddr2_ck_drv;
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unsigned int phy_lpddr2_dq_drv;
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unsigned int phy_lpddr2_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int phy_lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
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unsigned int phy_lpddr3_ck_drv;
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unsigned int phy_lpddr3_dq_drv;
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unsigned int phy_lpddr3_odt;
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unsigned int lpddr4_odt_dis_freq;
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unsigned int phy_lpddr4_odt_dis_freq;
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unsigned int lpddr4_drv;
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unsigned int lpddr4_dq_odt;
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unsigned int lpddr4_ca_odt;
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unsigned int phy_lpddr4_ca_drv;
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unsigned int phy_lpddr4_ck_cs_drv;
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unsigned int phy_lpddr4_dq_drv;
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unsigned int phy_lpddr4_odt;
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unsigned int ddr4_odt_dis_freq;
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unsigned int phy_ddr4_odt_dis_freq;
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unsigned int ddr4_drv;
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unsigned int ddr4_odt;
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unsigned int phy_ddr4_ca_drv;
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unsigned int phy_ddr4_ck_drv;
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unsigned int phy_ddr4_dq_drv;
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unsigned int phy_ddr4_odt;
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unsigned int ca_skew[15];
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unsigned int cs0_skew[44];
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unsigned int cs1_skew[44];
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unsigned int available;
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};
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static const char * const rk3128_dts_timing[] = {
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"ddr3_speed_bin",
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"pd_idle",
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@ -643,6 +795,61 @@ struct rockchip_dmcfreq {
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int (*set_auto_self_refresh)(u32 en);
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};
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/*
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* function: packaging de-skew setting to px30_ddr_dts_config_timing,
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* px30_ddr_dts_config_timing will pass to trust firmware, and
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* used direct to set register.
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* input: de_skew
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* output: tim
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*/
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static void px30_de_skew_set_2_reg(struct rk3328_ddr_de_skew_setting *de_skew,
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struct px30_ddr_dts_config_timing *tim)
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{
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u32 n;
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u32 offset;
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u32 shift;
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memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
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memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
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memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
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/* CA de-skew */
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for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
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offset = n / 2;
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shift = n % 2;
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/* 0 => 4; 1 => 0 */
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shift = (shift == 0) ? 4 : 0;
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tim->ca_skew[offset] &= ~(0xf << shift);
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tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
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}
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/* CS0 data de-skew */
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for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
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offset = ((n / 21) * 11) + ((n % 21) / 2);
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shift = ((n % 21) % 2);
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if ((n % 21) == 20)
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shift = 0;
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else
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/* 0 => 4; 1 => 0 */
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shift = (shift == 0) ? 4 : 0;
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tim->cs0_skew[offset] &= ~(0xf << shift);
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tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
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}
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/* CS1 data de-skew */
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for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
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offset = ((n / 21) * 11) + ((n % 21) / 2);
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shift = ((n % 21) % 2);
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if ((n % 21) == 20)
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shift = 0;
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else
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/* 0 => 4; 1 => 0 */
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shift = (shift == 0) ? 4 : 0;
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tim->cs1_skew[offset] &= ~(0xf << shift);
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tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
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}
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}
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/*
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* function: packaging de-skew setting to rk3328_ddr_dts_config_timing,
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* rk3328_ddr_dts_config_timing will pass to trust firmware, and
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@ -959,6 +1166,64 @@ static inline void reset_last_status(struct devfreq *devfreq)
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devfreq->last_status.busy_time = 1;
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}
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static void of_get_px30_timings(struct device *dev,
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struct device_node *np, uint32_t *timing)
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{
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struct device_node *np_tim;
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u32 *p;
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struct px30_ddr_dts_config_timing *dts_timing;
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struct rk3328_ddr_de_skew_setting *de_skew;
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int ret = 0;
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u32 i;
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dts_timing =
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(struct px30_ddr_dts_config_timing *)(timing +
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DTS_PAR_OFFSET / 4);
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np_tim = of_parse_phandle(np, "ddr_timing", 0);
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if (!np_tim) {
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ret = -EINVAL;
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goto end;
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}
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de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
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if (!de_skew) {
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ret = -ENOMEM;
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goto end;
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}
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p = (u32 *)dts_timing;
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for (i = 0; i < ARRAY_SIZE(px30_dts_timing); i++) {
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ret |= of_property_read_u32(np_tim, px30_dts_timing[i],
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p + i);
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}
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p = (u32 *)de_skew->ca_de_skew;
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for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
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ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
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p + i);
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}
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p = (u32 *)de_skew->cs0_de_skew;
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for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
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ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
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p + i);
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}
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p = (u32 *)de_skew->cs1_de_skew;
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for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
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ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
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p + i);
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}
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if (!ret)
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px30_de_skew_set_2_reg(de_skew, dts_timing);
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kfree(de_skew);
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end:
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if (!ret) {
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dts_timing->available = 1;
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} else {
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dts_timing->available = 0;
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dev_err(dev, "of_get_ddr_timings: fail\n");
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}
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of_node_put(np_tim);
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}
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static void of_get_rk3128_timings(struct device *dev,
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struct device_node *np, uint32_t *timing)
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{
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@ -1303,6 +1568,51 @@ static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
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return res.a0;
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}
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static int px30_dmc_init(struct platform_device *pdev,
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struct rockchip_dmcfreq *dmcfreq)
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{
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struct arm_smccc_res res;
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u32 size;
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res = sip_smc_dram(0, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
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dev_notice(&pdev->dev, "current ATF version 0x%lx!\n", res.a1);
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if (res.a0 || res.a1 < 0x101) {
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dev_err(&pdev->dev,
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"trusted firmware need to update or is invalid!\n");
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return -ENXIO;
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}
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dev_notice(&pdev->dev, "read tf version 0x%lx!\n", res.a1);
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/*
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* first 4KB is used for interface parameters
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* after 4KB * N is dts parameters
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*/
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size = sizeof(struct px30_ddr_dts_config_timing);
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res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
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SHARE_PAGE_TYPE_DDR);
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if (res.a0 != 0) {
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dev_err(&pdev->dev, "no ATF memory for init\n");
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return -ENOMEM;
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}
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ddr_psci_param = (struct share_params *)res.a1;
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of_get_px30_timings(&pdev->dev, pdev->dev.of_node,
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(uint32_t *)ddr_psci_param);
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res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_INIT);
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if (res.a0) {
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dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
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res.a0);
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return -ENOMEM;
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}
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dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
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return 0;
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}
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static int rk3128_dmc_init(struct platform_device *pdev,
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struct rockchip_dmcfreq *dmcfreq)
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{
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@ -1610,6 +1920,7 @@ static int rk3399_dmc_init(struct platform_device *pdev)
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}
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static const struct of_device_id rockchip_dmcfreq_of_match[] = {
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{ .compatible = "rockchip,px30-dmc", .data = px30_dmc_init },
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{ .compatible = "rockchip,rk3128-dmc", .data = rk3128_dmc_init },
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{ .compatible = "rockchip,rk3228-dmc", .data = rk3228_dmc_init },
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{ .compatible = "rockchip,rk3288-dmc", .data = rk3288_dmc_init },
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@ -16,6 +16,8 @@
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#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
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#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
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#define DDR2_DEFAULT (0)
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#define DDR3_800D (0) /* 5-5-5 */
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#define DDR3_800E (1) /* 6-6-6 */
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#define DDR3_1066E (2) /* 6-6-6 */
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132
include/dt-bindings/memory/px30-dram.h
Normal file
132
include/dt-bindings/memory/px30-dram.h
Normal file
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@ -0,0 +1,132 @@
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H
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#define _DT_BINDINGS_DRAM_ROCKCHIP_PX30_H
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#define DDR2_DS_FULL (0)
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#define DDR2_DS_REDUCE (1)
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#define DDR2_ODT_DIS (0)
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#define DDR2_ODT_50ohm (50) /* optional */
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#define DDR2_ODT_75ohm (75)
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#define DDR2_ODT_150ohm (150)
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#define DDR3_DS_34ohm (34)
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#define DDR3_DS_40ohm (40)
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#define DDR3_ODT_DIS (0)
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#define DDR3_ODT_40ohm (40)
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#define DDR3_ODT_60ohm (60)
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#define DDR3_ODT_120ohm (120)
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#define LP2_DS_34ohm (34)
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#define LP2_DS_40ohm (40)
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#define LP2_DS_48ohm (48)
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#define LP2_DS_60ohm (60)
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#define LP2_DS_68_6ohm (68) /* optional */
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#define LP2_DS_80ohm (80)
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#define LP2_DS_120ohm (120) /* optional */
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#define LP3_DS_34ohm (34)
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#define LP3_DS_40ohm (40)
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#define LP3_DS_48ohm (48)
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#define LP3_DS_60ohm (60)
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#define LP3_DS_80ohm (80)
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#define LP3_DS_34D_40U (3440)
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#define LP3_DS_40D_48U (4048)
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#define LP3_DS_34D_48U (3448)
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#define LP3_ODT_DIS (0)
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#define LP3_ODT_60ohm (60)
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#define LP3_ODT_120ohm (120)
|
||||
#define LP3_ODT_240ohm (240)
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||||
|
||||
#define LP4_PDDS_40ohm (40)
|
||||
#define LP4_PDDS_48ohm (48)
|
||||
#define LP4_PDDS_60ohm (60)
|
||||
#define LP4_PDDS_80ohm (80)
|
||||
#define LP4_PDDS_120ohm (120)
|
||||
#define LP4_PDDS_240ohm (240)
|
||||
|
||||
#define LP4_DQ_ODT_40ohm (40)
|
||||
#define LP4_DQ_ODT_48ohm (48)
|
||||
#define LP4_DQ_ODT_60ohm (60)
|
||||
#define LP4_DQ_ODT_80ohm (80)
|
||||
#define LP4_DQ_ODT_120ohm (120)
|
||||
#define LP4_DQ_ODT_240ohm (240)
|
||||
#define LP4_DQ_ODT_DIS (0)
|
||||
|
||||
#define LP4_CA_ODT_40ohm (40)
|
||||
#define LP4_CA_ODT_48ohm (48)
|
||||
#define LP4_CA_ODT_60ohm (60)
|
||||
#define LP4_CA_ODT_80ohm (80)
|
||||
#define LP4_CA_ODT_120ohm (120)
|
||||
#define LP4_CA_ODT_240ohm (240)
|
||||
#define LP4_CA_ODT_DIS (0)
|
||||
|
||||
#define DDR4_DS_34ohm (34)
|
||||
#define DDR4_DS_48ohm (48)
|
||||
#define DDR4_RTT_NOM_DIS (0)
|
||||
#define DDR4_RTT_NOM_60ohm (60)
|
||||
#define DDR4_RTT_NOM_120ohm (120)
|
||||
#define DDR4_RTT_NOM_40ohm (40)
|
||||
#define DDR4_RTT_NOM_240ohm (240)
|
||||
#define DDR4_RTT_NOM_48ohm (48)
|
||||
#define DDR4_RTT_NOM_80ohm (80)
|
||||
#define DDR4_RTT_NOM_34ohm (34)
|
||||
|
||||
#define PHY_DDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR3_RON_RTT_451ohm (1)
|
||||
#define PHY_DDR3_RON_RTT_225ohm (2)
|
||||
#define PHY_DDR3_RON_RTT_150ohm (3)
|
||||
#define PHY_DDR3_RON_RTT_112ohm (4)
|
||||
#define PHY_DDR3_RON_RTT_90ohm (5)
|
||||
#define PHY_DDR3_RON_RTT_75ohm (6)
|
||||
#define PHY_DDR3_RON_RTT_64ohm (7)
|
||||
#define PHY_DDR3_RON_RTT_56ohm (16)
|
||||
#define PHY_DDR3_RON_RTT_50ohm (17)
|
||||
#define PHY_DDR3_RON_RTT_45ohm (18)
|
||||
#define PHY_DDR3_RON_RTT_41ohm (19)
|
||||
#define PHY_DDR3_RON_RTT_37ohm (20)
|
||||
#define PHY_DDR3_RON_RTT_34ohm (21)
|
||||
#define PHY_DDR3_RON_RTT_33ohm (22)
|
||||
#define PHY_DDR3_RON_RTT_30ohm (23)
|
||||
#define PHY_DDR3_RON_RTT_28ohm (24)
|
||||
#define PHY_DDR3_RON_RTT_26ohm (25)
|
||||
#define PHY_DDR3_RON_RTT_25ohm (26)
|
||||
#define PHY_DDR3_RON_RTT_23ohm (27)
|
||||
#define PHY_DDR3_RON_RTT_22ohm (28)
|
||||
#define PHY_DDR3_RON_RTT_21ohm (29)
|
||||
#define PHY_DDR3_RON_RTT_20ohm (30)
|
||||
#define PHY_DDR3_RON_RTT_19ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_480ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_240ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_160ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_120ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_96ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_80ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_68ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_60ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_53ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_48ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_43ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_40ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_37ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_34ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_32ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_30ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_28ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_26ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_25ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_24ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_22ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_21ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_2_RON_RTT_20ohm (31)
|
||||
|
||||
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_PX30_H*/
|
||||
Loading…
Reference in New Issue
Block a user