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arm64: dts: qcom: sm8650: add CPU cache size properties

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Add the L1 cache size and its line size (cache-size and
cache-line-size) with the corresponding L1-I cache and L1-D cache.

L1 cache is unified, but clidr_el1 register (get_cache_type) tells that
L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and
d-cache-line-size and cache-line-size of L3 cache is specified.

All cache line sizes were confirmed by checking ccsidr_el1.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20260615-topic-sm8650-upstream-cpu-props-v3-2-eeb6e9fa7581@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Neil Armstrong 2026-06-15 18:48:57 +02:00 committed by Bjorn Andersson
parent bb016ddb90
commit 884ff1172a
1 changed files with 56 additions and 0 deletions
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56
arch/arm64/boot/dts/qcom/sm8650.dtsi
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@ -75,6 +75,11 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a520";
reg = <0 0>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
clocks = <&cpufreq_hw 0>;
power-domains = <&cpu_pd0>;
@ -103,11 +108,15 @@ l2_0: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
cache-size = <524288>;
cache-line-size = <64>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
cache-size = <12582912>;
cache-line-size = <64>;
};
};
};
@ -117,6 +126,11 @@ cpu1: cpu@100 {
compatible = "arm,cortex-a520";
reg = <0 0x100>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
clocks = <&cpufreq_hw 0>;
power-domains = <&cpu_pd1>;
@ -146,6 +160,11 @@ cpu2: cpu@200 {
compatible = "arm,cortex-a720";
reg = <0 0x200>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd2>;
@ -174,6 +193,8 @@ l2_200: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
cache-size = <524288>;
cache-line-size = <64>;
};
};
@ -182,6 +203,11 @@ cpu3: cpu@300 {
compatible = "arm,cortex-a720";
reg = <0 0x300>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd3>;
@ -210,6 +236,8 @@ l2_300: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
cache-size = <524288>;
cache-line-size = <64>;
};
};
@ -218,6 +246,11 @@ cpu4: cpu@400 {
compatible = "arm,cortex-a720";
reg = <0 0x400>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
clocks = <&cpufreq_hw 3>;
power-domains = <&cpu_pd4>;
@ -246,6 +279,8 @@ l2_400: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
cache-size = <524288>;
cache-line-size = <64>;
};
};
@ -254,6 +289,11 @@ cpu5: cpu@500 {
compatible = "arm,cortex-a720";
reg = <0 0x500>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
clocks = <&cpufreq_hw 1>;
power-domains = <&cpu_pd5>;
@ -282,6 +322,8 @@ l2_500: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
cache-size = <524288>;
cache-line-size = <64>;
};
};
@ -290,6 +332,11 @@ cpu6: cpu@600 {
compatible = "arm,cortex-a720";
reg = <0 0x600>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
clocks = <&cpufreq_hw 1>;
power-domains = <&cpu_pd6>;
@ -318,6 +365,8 @@ l2_600: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
cache-size = <524288>;
cache-line-size = <64>;
};
};
@ -326,6 +375,11 @@ cpu7: cpu@700 {
compatible = "arm,cortex-x4";
reg = <0 0x700>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
clocks = <&cpufreq_hw 2>;
power-domains = <&cpu_pd7>;
@ -354,6 +408,8 @@ l2_700: l2-cache {
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
cache-size = <2097152>;
cache-line-size = <64>;
};
};