From afae0fa7c6b163339a5d357942b89956a0820e45 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Mon, 29 Jun 2026 15:10:58 -0700 Subject: [PATCH 1/8] cxl/test: Add test for module parameters Add a test for module paraters during module init to make sure that only one is activated. [dj: Dropped counting fail_autoassemble modparm. (Alison) ] Suggested-by: Alison Schofield Tested-by: Alison Schofield Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260629221104.3891733-2-dave.jiang@intel.com Signed-off-by: Dave Jiang --- tools/testing/cxl/test/cxl.c | 18 ++++++++++++++++++ tools/testing/cxl/test/hmem_test.c | 3 ++- tools/testing/cxl/test/mock.h | 2 ++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index ef92dd35e030..057724f27c6b 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -1827,11 +1827,29 @@ static struct attribute *cxl_acpi_attrs[] = { }; ATTRIBUTE_GROUPS(cxl_acpi); +static bool __init have_multiple_modparms(void) +{ + int count = 0; + + if (interleave_arithmetic) + count++; + if (extended_linear_cache) + count++; + if (hmem_test) + count++; + + return count > 1; +} + static __init int cxl_test_init(void) { int rc, i; struct range mappable; + /* Enforce a single module param active at a time */ + if (have_multiple_modparms()) + return -EINVAL; + if (!IS_ALIGNED(mock_auto_region_size, PMD_SIZE)) { pr_err_once("mock_auto_region_size %d must be PMD-aligned\n", mock_auto_region_size); diff --git a/tools/testing/cxl/test/hmem_test.c b/tools/testing/cxl/test/hmem_test.c index 3a1a089e1721..0fa00f7e16db 100644 --- a/tools/testing/cxl/test/hmem_test.c +++ b/tools/testing/cxl/test/hmem_test.c @@ -3,8 +3,9 @@ #include #include #include "../../../drivers/dax/bus.h" +#include "mock.h" -static bool hmem_test; +bool hmem_test; static void hmem_test_work(struct work_struct *work) { diff --git a/tools/testing/cxl/test/mock.h b/tools/testing/cxl/test/mock.h index 4f57dc80ae7d..846d7c5d6eaa 100644 --- a/tools/testing/cxl/test/mock.h +++ b/tools/testing/cxl/test/mock.h @@ -5,6 +5,8 @@ #include #include +extern bool hmem_test; + struct cxl_mock_ops { struct list_head list; bool (*is_mock_adev)(struct acpi_device *dev); From fc8fc576d909b0336a6f8053d68989c2811aeec0 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Mon, 29 Jun 2026 15:10:59 -0700 Subject: [PATCH 2/8] cxl/test: Add type2 support for mock CFMWS0 Add a module parameter 'type2_test' for triggering type2 test support in cxl_test. Setup the CFMWS0 configuration to be type2 when 'type2_test' is set. Tested-by: Alison Schofield Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260629221104.3891733-3-dave.jiang@intel.com Signed-off-by: Dave Jiang --- tools/testing/cxl/test/cxl.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 057724f27c6b..3eb9998360f5 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -17,6 +17,7 @@ static int interleave_arithmetic; static bool extended_linear_cache; static bool fail_autoassemble; +static bool type2_test; #define FAKE_QTG_ID 42 @@ -384,6 +385,19 @@ static struct { }, }; +static struct acpi_cedt_cfmws type2_cfmws0 = { + .header = { + .type = ACPI_CEDT_TYPE_CFMWS, + .length = sizeof(mock_cedt.cfmws0), + }, + .interleave_ways = 0, + .granularity = 4, + .restrictions = ACPI_CEDT_CFMWS_RESTRICT_DEVMEM | + ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, + .qtg_id = FAKE_QTG_ID, + .window_size = SZ_256M * 4, +}; + struct acpi_cedt_cfmws *mock_cfmws[] = { [0] = &mock_cedt.cfmws0.cfmws, [1] = &mock_cedt.cfmws1.cfmws, @@ -476,6 +490,11 @@ static void cfmws_elc_update(struct acpi_cedt_cfmws *window, int index) window->window_size = mock_auto_region_size * 2; } +static void update_type2_cfmws(void) +{ + memcpy(&mock_cedt.cfmws0.cfmws, &type2_cfmws0, sizeof(type2_cfmws0)); +} + static int populate_cedt(void) { struct cxl_mock_res *res; @@ -497,11 +516,15 @@ static int populate_cedt(void) chbs->length = size; } + if (type2_test) + update_type2_cfmws(); + for (i = cfmws_start; i <= cfmws_end; i++) { struct acpi_cedt_cfmws *window = mock_cfmws[i]; int align = SZ_256M; - cfmws_elc_update(window, i); + if (i == 0 && !type2_test) + cfmws_elc_update(window, i); if (window->restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) align = max_t(int, SZ_256M, PMD_SIZE); res = alloc_mock_res(window->window_size, align); @@ -1837,6 +1860,8 @@ static bool __init have_multiple_modparms(void) count++; if (hmem_test) count++; + if (type2_test) + count++; return count > 1; } @@ -2067,6 +2092,8 @@ module_param(extended_linear_cache, bool, 0444); MODULE_PARM_DESC(extended_linear_cache, "Enable extended linear cache support"); module_param(fail_autoassemble, bool, 0444); MODULE_PARM_DESC(fail_autoassemble, "Simulate missing member of an auto-region"); +module_param(type2_test, bool, 0444); +MODULE_PARM_DESC(type2_test, "Enable type 2 support testing"); module_init(cxl_test_init); module_exit(cxl_test_exit); MODULE_LICENSE("GPL v2"); From a6d37152d284a49249a545861d1094cb678b5d32 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Mon, 29 Jun 2026 15:11:00 -0700 Subject: [PATCH 3/8] cxl/test: Refactor platform device enumerations Split all the host bridges, rootports, upstream and downstream ports enumerations to separate helper functions. This should make adding type2 hierarchy easier later on. Tested-by: Alison Schofield Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260629221104.3891733-4-dave.jiang@intel.com Signed-off-by: Dave Jiang --- tools/testing/cxl/test/cxl.c | 312 ++++++++++++++++++++++++----------- 1 file changed, 214 insertions(+), 98 deletions(-) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 3eb9998360f5..504c737be146 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -1866,10 +1866,204 @@ static bool __init have_multiple_modparms(void) return count > 1; } +static void host_bridges_remove(void) +{ + int i; + + for (i = ARRAY_SIZE(cxl_host_bridge) - 1; i >= 0; i--) { + struct platform_device *pdev = cxl_host_bridge[i]; + + if (!pdev) + continue; + + sysfs_remove_link(&pdev->dev.kobj, "physical_node"); + platform_device_unregister(cxl_host_bridge[i]); + } +} + +static int host_bridges_populate(void) +{ + int rc = 0; + + for (int i = 0; i < ARRAY_SIZE(cxl_host_bridge); i++) { + struct acpi_device *adev = &host_bridge[i]; + struct platform_device *pdev; + + pdev = platform_device_alloc("cxl_host_bridge", i); + if (!pdev) { + rc = -ENOMEM; + goto err_bridge; + } + + mock_companion(adev, &pdev->dev); + rc = cxl_mock_platform_device_add(pdev, &cxl_host_bridge[i]); + if (rc) + goto err_bridge; + + mock_pci_bus[i].bridge = &pdev->dev; + rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj, + "physical_node"); + if (rc) + goto err_bridge; + } + + return 0; + +err_bridge: + host_bridges_remove(); + return rc; +} + +static void cxl_rootports_remove(void) +{ + for (int i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--) { + struct platform_device *pdev = cxl_root_port[i]; + + if (!pdev) + continue; + + platform_device_unregister(pdev); + } +} + +static int cxl_rootports_populate(void) +{ + int rc = 0; + + for (int i = 0; i < ARRAY_SIZE(cxl_root_port); i++) { + struct platform_device *bridge = + cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)]; + struct platform_device *pdev; + + pdev = platform_device_alloc("cxl_root_port", i); + if (!pdev) { + rc = -ENOMEM; + goto err_port; + } + + pdev->dev.parent = &bridge->dev; + + rc = cxl_mock_platform_device_add(pdev, &cxl_root_port[i]); + if (rc) + goto err_port; + } + + return 0; + +err_port: + cxl_rootports_remove(); + return rc; +} + +static void cxl_usps_remove(void) +{ + for (int i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--) { + struct platform_device *pdev = cxl_switch_uport[i]; + + if (!pdev) + continue; + + platform_device_unregister(cxl_switch_uport[i]); + } +} + +static int cxl_usps_populate(void) +{ + int rc = 0; + + for (int i = 0; i < ARRAY_SIZE(cxl_switch_uport); i++) { + struct platform_device *root_port = cxl_root_port[i]; + struct platform_device *pdev; + + pdev = platform_device_alloc("cxl_switch_uport", i); + if (!pdev) { + rc = -ENOMEM; + goto err_uport; + } + + pdev->dev.parent = &root_port->dev; + + rc = cxl_mock_platform_device_add(pdev, &cxl_switch_uport[i]); + if (rc) + goto err_uport; + } + + return 0; + +err_uport: + cxl_usps_remove(); + return rc; +} + +static void cxl_dsps_remove(void) +{ + for (int i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--) { + struct platform_device *pdev = cxl_switch_dport[i]; + + if (!pdev) + continue; + + platform_device_unregister(cxl_switch_dport[i]); + } +} + + +static int cxl_dsps_populate(void) +{ + int rc = 0; + + for (int i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++) { + struct platform_device *uport = + cxl_switch_uport[i % ARRAY_SIZE(cxl_switch_uport)]; + struct platform_device *pdev; + + pdev = platform_device_alloc("cxl_switch_dport", i); + if (!pdev) { + rc = -ENOMEM; + goto err_dport; + } + pdev->dev.parent = &uport->dev; + + rc = cxl_mock_platform_device_add(pdev, &cxl_switch_dport[i]); + if (rc) + goto err_dport; + } + + return 0; + +err_dport: + cxl_dsps_remove(); + return rc; +} + +static void cxl_switches_remove(void) +{ + cxl_dsps_remove(); + cxl_usps_remove(); +} + +static int cxl_switches_populate(void) +{ + int rc; + + BUILD_BUG_ON(ARRAY_SIZE(cxl_switch_uport) != ARRAY_SIZE(cxl_root_port)); + rc = cxl_usps_populate(); + if (rc) + return rc; + + rc = cxl_dsps_populate(); + if (rc) { + cxl_usps_remove(); + return rc; + } + + return 0; +} + static __init int cxl_test_init(void) { - int rc, i; struct range mappable; + int rc; /* Enforce a single module param active at a time */ if (have_multiple_modparms()) @@ -1915,74 +2109,21 @@ static __init int cxl_test_init(void) if (rc) goto err_populate; - for (i = 0; i < ARRAY_SIZE(cxl_host_bridge); i++) { - struct acpi_device *adev = &host_bridge[i]; - struct platform_device *pdev; + rc = host_bridges_populate(); + if (rc) + goto err_populate; - pdev = platform_device_alloc("cxl_host_bridge", i); - if (!pdev) - goto err_bridge; + rc = cxl_rootports_populate(); + if (rc) + goto err_host_bridges; - mock_companion(adev, &pdev->dev); - rc = cxl_mock_platform_device_add(pdev, &cxl_host_bridge[i]); - if (rc) - goto err_bridge; - - mock_pci_bus[i].bridge = &pdev->dev; - rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj, - "physical_node"); - if (rc) - goto err_bridge; - } - - for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) { - struct platform_device *bridge = - cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)]; - struct platform_device *pdev; - - pdev = platform_device_alloc("cxl_root_port", i); - if (!pdev) - goto err_port; - pdev->dev.parent = &bridge->dev; - - rc = cxl_mock_platform_device_add(pdev, &cxl_root_port[i]); - if (rc) - goto err_port; - } - - BUILD_BUG_ON(ARRAY_SIZE(cxl_switch_uport) != ARRAY_SIZE(cxl_root_port)); - for (i = 0; i < ARRAY_SIZE(cxl_switch_uport); i++) { - struct platform_device *root_port = cxl_root_port[i]; - struct platform_device *pdev; - - pdev = platform_device_alloc("cxl_switch_uport", i); - if (!pdev) - goto err_uport; - pdev->dev.parent = &root_port->dev; - - rc = cxl_mock_platform_device_add(pdev, &cxl_switch_uport[i]); - if (rc) - goto err_uport; - } - - for (i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++) { - struct platform_device *uport = - cxl_switch_uport[i % ARRAY_SIZE(cxl_switch_uport)]; - struct platform_device *pdev; - - pdev = platform_device_alloc("cxl_switch_dport", i); - if (!pdev) - goto err_dport; - pdev->dev.parent = &uport->dev; - - rc = cxl_mock_platform_device_add(pdev, &cxl_switch_dport[i]); - if (rc) - goto err_dport; - } + rc = cxl_switches_populate(); + if (rc) + goto err_root_ports; rc = cxl_single_topo_init(); if (rc) - goto err_dport; + goto err_switches; rc = cxl_rch_topo_init(); if (rc) @@ -2018,24 +2159,12 @@ static __init int cxl_test_init(void) cxl_rch_topo_exit(); err_single: cxl_single_topo_exit(); -err_dport: - for (i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--) - platform_device_unregister(cxl_switch_dport[i]); -err_uport: - for (i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--) - platform_device_unregister(cxl_switch_uport[i]); -err_port: - for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--) - platform_device_unregister(cxl_root_port[i]); -err_bridge: - for (i = ARRAY_SIZE(cxl_host_bridge) - 1; i >= 0; i--) { - struct platform_device *pdev = cxl_host_bridge[i]; - - if (!pdev) - continue; - sysfs_remove_link(&pdev->dev.kobj, "physical_node"); - platform_device_unregister(cxl_host_bridge[i]); - } +err_switches: + cxl_switches_remove(); +err_root_ports: + cxl_rootports_remove(); +err_host_bridges: + host_bridges_remove(); err_populate: depopulate_all_mock_resources(); err_gen_pool_add: @@ -2058,27 +2187,14 @@ static void free_decoder_registry(void) static __exit void cxl_test_exit(void) { - int i; - hmem_test_exit(); cxl_mem_exit(); platform_device_unregister(cxl_acpi); cxl_rch_topo_exit(); cxl_single_topo_exit(); - for (i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--) - platform_device_unregister(cxl_switch_dport[i]); - for (i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--) - platform_device_unregister(cxl_switch_uport[i]); - for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--) - platform_device_unregister(cxl_root_port[i]); - for (i = ARRAY_SIZE(cxl_host_bridge) - 1; i >= 0; i--) { - struct platform_device *pdev = cxl_host_bridge[i]; - - if (!pdev) - continue; - sysfs_remove_link(&pdev->dev.kobj, "physical_node"); - platform_device_unregister(cxl_host_bridge[i]); - } + cxl_switches_remove(); + cxl_rootports_remove(); + host_bridges_remove(); depopulate_all_mock_resources(); gen_pool_destroy(cxl_mock_pool); unregister_cxl_mock_ops(&cxl_mock_ops); From 6b2e585142e68b4af821a1eca4d1e8d54bd49bb8 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Mon, 29 Jun 2026 15:11:01 -0700 Subject: [PATCH 4/8] cxl/test: Add hierarchy enumeration support for type2 device Add enumeration of type2 device hierarchy in cxl-test. The type2 device is setup to be directly attached to a root port instead of rp -> switch -> device that type3 hierarchy is setup.. Tested-by: Alison Schofield Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260629221104.3891733-5-dave.jiang@intel.com Signed-off-by: Dave Jiang --- tools/testing/cxl/test/cxl.c | 232 ++++++++++++++++++++++++++++------- 1 file changed, 189 insertions(+), 43 deletions(-) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 504c737be146..ab84551b1136 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -28,6 +28,7 @@ static bool type2_test; #define NR_CXL_SWITCH_PORTS 2 #define NR_CXL_PORT_DECODERS 8 #define NR_BRIDGES (NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + NR_CXL_RCH) +#define NR_CXL_TYPE2_ACCEL 1 #define MOCK_AUTO_REGION_SIZE_DEFAULT SZ_512M static int mock_auto_region_size = MOCK_AUTO_REGION_SIZE_DEFAULT; @@ -1747,19 +1748,93 @@ static void cxl_single_topo_exit(void) } } -static void cxl_mem_exit(void) +static void cxl_type3_mem_exit(void) { + struct platform_device *pdev; int i; - for (i = ARRAY_SIZE(cxl_rcd) - 1; i >= 0; i--) + for (i = ARRAY_SIZE(cxl_rcd) - 1; i >= 0; i--) { + pdev = cxl_rcd[i]; + if (!pdev) + continue; platform_device_unregister(cxl_rcd[i]); - for (i = ARRAY_SIZE(cxl_mem_single) - 1; i >= 0; i--) + } + + for (i = ARRAY_SIZE(cxl_mem_single) - 1; i >= 0; i--) { + pdev = cxl_mem_single[i]; + if (!pdev) + continue; platform_device_unregister(cxl_mem_single[i]); - for (i = ARRAY_SIZE(cxl_mem) - 1; i >= 0; i--) - platform_device_unregister(cxl_mem[i]); + } + + for (i = ARRAY_SIZE(cxl_mem) - 1; i >= 0; i--) { + pdev = cxl_mem[i]; + if (!pdev) + continue; + platform_device_unregister(pdev); + } } -static int cxl_mem_init(void) +static void cxl_type2_mem_exit(void) +{ + for (int i = NR_CXL_TYPE2_ACCEL - 1; i >= 0; i--) { + struct platform_device *pdev = cxl_mem[i]; + + if (!pdev) + continue; + platform_device_unregister(pdev); + } +} + +static void cxl_mem_exit(void) +{ + if (type2_test) { + cxl_type2_mem_exit(); + return; + } + + cxl_type3_mem_exit(); +} + +static int cxl_type2_mem_init(void) +{ + int i, rc; + + for (i = 0; i < NR_CXL_TYPE2_ACCEL; i++) { + struct platform_device *dport = cxl_root_port[i]; + struct platform_device *pdev; + + pdev = platform_device_alloc("cxl_type2_accel", i); + if (!pdev) { + rc = -ENOMEM; + goto err_mem; + } + pdev->dev.parent = &dport->dev; + set_dev_node(&pdev->dev, i % 2); + + rc = platform_device_add(pdev); + if (rc) { + rc = -ENOMEM; + platform_device_put(pdev); + goto err_mem; + } + cxl_mem[i] = pdev; + } + + return 0; + +err_mem: + for (i = NR_CXL_TYPE2_ACCEL - 1; i >= 0; i--) { + struct platform_device *pdev = cxl_mem[i]; + + if (!pdev) + continue; + platform_device_unregister(pdev); + } + return rc; +} + +static int cxl_type3_mem_init(void) { int i, rc; @@ -1768,8 +1843,10 @@ static int cxl_mem_init(void) struct platform_device *pdev; pdev = platform_device_alloc("cxl_mem", i); - if (!pdev) + if (!pdev) { + rc = -ENOMEM; goto err_mem; + } pdev->dev.parent = &dport->dev; set_dev_node(&pdev->dev, i % 2); @@ -1783,8 +1860,10 @@ static int cxl_mem_init(void) struct platform_device *pdev; pdev = platform_device_alloc("cxl_mem", NR_MEM_MULTI + i); - if (!pdev) + if (!pdev) { + rc = -ENOMEM; goto err_single; + } pdev->dev.parent = &dport->dev; set_dev_node(&pdev->dev, i % 2); @@ -1799,8 +1878,10 @@ static int cxl_mem_init(void) struct platform_device *pdev; pdev = platform_device_alloc("cxl_rcd", idx); - if (!pdev) + if (!pdev) { + rc = -ENOMEM; goto err_rcd; + } pdev->dev.parent = &rch->dev; set_dev_node(&pdev->dev, i % 2); @@ -1823,6 +1904,13 @@ static int cxl_mem_init(void) return rc; } +static int cxl_mem_init(void) +{ + if (type2_test) + return cxl_type2_mem_init(); + return cxl_type3_mem_init(); +} + static ssize_t decoder_reset_preserve_registry_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -2060,6 +2148,92 @@ static int cxl_switches_populate(void) return 0; } +static void cxl_type2_topo_exit(void) +{ + cxl_rootports_remove(); + host_bridges_remove(); +} + +static int cxl_type2_topo_init(void) +{ + int rc; + + rc = host_bridges_populate(); + if (rc) + return rc; + + rc = cxl_rootports_populate(); + if (rc) { + host_bridges_remove(); + return rc; + } + + return 0; +} + +static void cxl_type3_topo_exit(void) +{ + cxl_rch_topo_exit(); + cxl_single_topo_exit(); + cxl_switches_remove(); + cxl_rootports_remove(); + host_bridges_remove(); +} + +static int cxl_type3_topo_init(void) +{ + int rc; + + rc = host_bridges_populate(); + if (rc) + return rc; + + rc = cxl_rootports_populate(); + if (rc) + goto err_host_bridges; + + rc = cxl_switches_populate(); + if (rc) + goto err_root_ports; + + rc = cxl_single_topo_init(); + if (rc) + goto err_switches; + + rc = cxl_rch_topo_init(); + if (rc) + goto err_single; + + return 0; + +err_single: + cxl_single_topo_exit(); +err_switches: + cxl_switches_remove(); +err_root_ports: + cxl_rootports_remove(); +err_host_bridges: + host_bridges_remove(); + return rc; +} + +static void cxl_topo_exit(void) +{ + if (type2_test) { + cxl_type2_topo_exit(); + return; + } + + cxl_type3_topo_exit(); +} + +static int cxl_topo_init(void) +{ + if (type2_test) + return cxl_type2_topo_init(); + return cxl_type3_topo_init(); +} + static __init int cxl_test_init(void) { struct range mappable; @@ -2109,29 +2283,13 @@ static __init int cxl_test_init(void) if (rc) goto err_populate; - rc = host_bridges_populate(); + rc = cxl_topo_init(); if (rc) goto err_populate; - rc = cxl_rootports_populate(); - if (rc) - goto err_host_bridges; - - rc = cxl_switches_populate(); - if (rc) - goto err_root_ports; - - rc = cxl_single_topo_init(); - if (rc) - goto err_switches; - - rc = cxl_rch_topo_init(); - if (rc) - goto err_single; - cxl_acpi = platform_device_alloc("cxl_acpi", 0); if (!cxl_acpi) - goto err_rch; + goto err_topo; mock_companion(&acpi0017_mock, &cxl_acpi->dev); acpi0017_mock.dev.bus = &platform_bus_type; @@ -2139,7 +2297,7 @@ static __init int cxl_test_init(void) rc = cxl_mock_platform_device_add(cxl_acpi, NULL); if (rc) - goto err_rch; + goto err_topo; rc = cxl_mem_init(); if (rc) @@ -2155,16 +2313,8 @@ static __init int cxl_test_init(void) cxl_mem_exit(); err_root: platform_device_unregister(cxl_acpi); -err_rch: - cxl_rch_topo_exit(); -err_single: - cxl_single_topo_exit(); -err_switches: - cxl_switches_remove(); -err_root_ports: - cxl_rootports_remove(); -err_host_bridges: - host_bridges_remove(); +err_topo: + cxl_topo_exit(); err_populate: depopulate_all_mock_resources(); err_gen_pool_add: @@ -2190,11 +2340,7 @@ static __exit void cxl_test_exit(void) hmem_test_exit(); cxl_mem_exit(); platform_device_unregister(cxl_acpi); - cxl_rch_topo_exit(); - cxl_single_topo_exit(); - cxl_switches_remove(); - cxl_rootports_remove(); - host_bridges_remove(); + cxl_topo_exit(); depopulate_all_mock_resources(); gen_pool_destroy(cxl_mock_pool); unregister_cxl_mock_ops(&cxl_mock_ops); From 98ba41c3236b9a3bad206dbd9cf18c98ced75726 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Mon, 29 Jun 2026 15:11:02 -0700 Subject: [PATCH 5/8] cxl/test: Propagate -ENOMEM on platform_device_alloc() failures Set rc = -ENOMEM at every platform_device_alloc() failure site in cxl_rch_topo_init(), cxl_single_topo_init() and cxl_test_init() so the failure is propagated and the module load aborts cleanly. The cxl_acpi allocation site originates in the commit below, while the host-bridge/root-port/uport/dport allocation sites fixed here were added later in the single-host and RCH topology configs. Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy") Fixes: e41c8452b9b2 ("tools/testing/cxl: Add a single-port host-bridge regression config") Fixes: c9435dbee119 ("tools/testing/cxl: Add an RCH topology") Assisted-by: Claude:claude-opus-4-8 Tested-by: Alison Schofield Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260629221104.3891733-6-dave.jiang@intel.com Signed-off-by: Dave Jiang --- tools/testing/cxl/test/cxl.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index ab84551b1136..5d766b8cdd40 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -1587,8 +1587,10 @@ static __init int cxl_rch_topo_init(void) struct platform_device *pdev; pdev = platform_device_alloc("cxl_host_bridge", idx); - if (!pdev) + if (!pdev) { + rc = -ENOMEM; goto err_bridge; + } mock_companion(adev, &pdev->dev); rc = cxl_mock_platform_device_add(pdev, &cxl_rch[i]); @@ -1642,8 +1644,10 @@ static __init int cxl_single_topo_init(void) pdev = platform_device_alloc("cxl_host_bridge", NR_CXL_HOST_BRIDGES + i); - if (!pdev) + if (!pdev) { + rc = -ENOMEM; goto err_bridge; + } mock_companion(adev, &pdev->dev); rc = cxl_mock_platform_device_add(pdev, &cxl_hb_single[i]); @@ -1664,8 +1668,10 @@ static __init int cxl_single_topo_init(void) pdev = platform_device_alloc("cxl_root_port", NR_MULTI_ROOT + i); - if (!pdev) + if (!pdev) { + rc = -ENOMEM; goto err_port; + } pdev->dev.parent = &bridge->dev; rc = cxl_mock_platform_device_add(pdev, &cxl_root_single[i]); @@ -1679,8 +1685,10 @@ static __init int cxl_single_topo_init(void) pdev = platform_device_alloc("cxl_switch_uport", NR_MULTI_ROOT + i); - if (!pdev) + if (!pdev) { + rc = -ENOMEM; goto err_uport; + } pdev->dev.parent = &root_port->dev; rc = cxl_mock_platform_device_add(pdev, &cxl_swu_single[i]); @@ -1695,8 +1703,10 @@ static __init int cxl_single_topo_init(void) pdev = platform_device_alloc("cxl_switch_dport", i + NR_MEM_MULTI); - if (!pdev) + if (!pdev) { + rc = -ENOMEM; goto err_dport; + } pdev->dev.parent = &uport->dev; rc = cxl_mock_platform_device_add(pdev, &cxl_swd_single[i]); @@ -2288,8 +2298,10 @@ static __init int cxl_test_init(void) goto err_populate; cxl_acpi = platform_device_alloc("cxl_acpi", 0); - if (!cxl_acpi) + if (!cxl_acpi) { + rc = -ENOMEM; goto err_topo; + } mock_companion(&acpi0017_mock, &cxl_acpi->dev); acpi0017_mock.dev.bus = &platform_bus_type; From b3df5a5a38c32e1d161f92234ab70c39d640ea41 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Mon, 29 Jun 2026 15:11:03 -0700 Subject: [PATCH 6/8] cxl/test: Fixup hdm init for auto region to support type2 Add support to setup initialization of decoders in order to support type2 auto region. Reviewed-by: Alison Schofield Tested-by: Alison Schofield Link: https://patch.msgid.link/20260629221104.3891733-7-dave.jiang@intel.com Signed-off-by: Dave Jiang --- tools/testing/cxl/test/cxl.c | 263 ++++++++++++++++++++++++++--------- 1 file changed, 194 insertions(+), 69 deletions(-) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 5d766b8cdd40..8ab2ce1262f3 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -1084,74 +1084,26 @@ static int first_decoder(struct device *dev, const void *data) return 0; } -/* - * Initialize a decoder during HDM enumeration. - * - * If a saved registry entry exists: - * - enabled decoders are restored from the saved programming - * - disabled decoders are initialized in a clean disabled state - * - * If no registry entry exists the decoder follows the normal mock - * initialization path, including the special auto-region setup for - * the first endpoints under host-bridge0. - * - * Returns true if decoder state was restored from the registry. In - * that case the saved decode configuration (including target mapping) - * has already been applied and the map_targets() is skipped. - */ -static bool mock_init_hdm_decoder(struct cxl_decoder *cxld) +enum cxld_init_type { + MOCK_DECODER_INIT_DEFAULT, + MOCK_DECODER_INIT_SAVED, + MOCK_DECODER_INIT_TYPE3_AUTO, + MOCK_DECODER_INIT_TYPE2_AUTO, +}; + +static enum cxld_init_type get_decoder_init_type(struct cxl_decoder *cxld, + struct platform_device *pdev, + bool hb0, + struct cxl_test_decoder **td) { - struct acpi_cedt_cfmws *window = mock_cfmws[0]; - struct platform_device *pdev = NULL; - struct cxl_endpoint_decoder *cxled; - struct cxl_switch_decoder *cxlsd; - struct cxl_port *port, *iter; - struct cxl_test_decoder *td; - struct cxl_memdev *cxlmd; - struct cxl_dport *dport; - struct device *dev; - bool hb0 = false; - u64 base; - int i; + struct cxl_test_decoder *found_td = cxld_registry_find(cxld); - if (is_endpoint_decoder(&cxld->dev)) { - cxled = to_cxl_endpoint_decoder(&cxld->dev); - cxlmd = cxled_to_memdev(cxled); - WARN_ON(!dev_is_platform(cxlmd->dev.parent)); - pdev = to_platform_device(cxlmd->dev.parent); - - /* check is endpoint is attach to host-bridge0 */ - port = cxled_to_port(cxled); - do { - if (port->uport_dev == &cxl_host_bridge[0]->dev) { - hb0 = true; - break; - } - if (is_cxl_port(port->dev.parent)) - port = to_cxl_port(port->dev.parent); - else - port = NULL; - } while (port); - port = cxled_to_port(cxled); - } else { - port = to_cxl_port(cxld->dev.parent); + if (found_td) { + *td = found_td; + return MOCK_DECODER_INIT_SAVED; } - td = cxld_registry_find(cxld); - if (td) { - bool enabled; - - if (is_switch_decoder(&cxld->dev)) - enabled = td->cxlsd.cxld.flags & CXL_DECODER_F_ENABLE; - else - enabled = td->cxled.cxld.flags & CXL_DECODER_F_ENABLE; - - if (enabled) - return !cxld_registry_restore(cxld, td); - - init_disabled_mock_decoder(cxld); - return false; - } + *td = NULL; /* * The first decoder on the first 2 devices on the first switch @@ -1162,15 +1114,119 @@ static bool mock_init_hdm_decoder(struct cxl_decoder *cxld) * See 'cxl list -BMPu -m cxl_mem.0,cxl_mem.4' */ if (!is_endpoint_decoder(&cxld->dev) || !hb0 || pdev->id % 4 || - pdev->id > 4 || cxld->id > 0) { - default_mock_decoder(cxld); - return false; - } + pdev->id > 4 || cxld->id > 0) + return MOCK_DECODER_INIT_DEFAULT; + + return type2_test ? MOCK_DECODER_INIT_TYPE2_AUTO : + MOCK_DECODER_INIT_TYPE3_AUTO; +} + +static bool mock_decoder_handle_saved(struct cxl_decoder *cxld, struct cxl_test_decoder *td) +{ + bool enabled; + + if (is_switch_decoder(&cxld->dev)) + enabled = td->cxlsd.cxld.flags & CXL_DECODER_F_ENABLE; + else + enabled = td->cxled.cxld.flags & CXL_DECODER_F_ENABLE; + + if (enabled) + return !cxld_registry_restore(cxld, td); + + init_disabled_mock_decoder(cxld); + return false; +} + +static void mock_init_hdm_type2_cxled(struct cxl_endpoint_decoder *cxled, + struct cxl_port *port) +{ + struct acpi_cedt_cfmws *window = mock_cfmws[0]; + struct cxl_decoder *cxld = &cxled->cxld; + struct cxl_switch_decoder *cxlsd; + struct cxl_dport *dport; + struct cxl_port *root_port; + struct device *dev; + u64 base; + + base = window->base_hpa; + cxld->hpa_range = (struct range) { + .start = base, + .end = base + mock_auto_region_size - 1, + }; + + cxld->interleave_ways = 1; + eig_to_granularity(window->granularity, &cxld->interleave_granularity); + cxld->target_type = CXL_DECODER_DEVMEM; + cxld->flags = CXL_DECODER_F_ENABLE; + cxled->state = CXL_DECODER_STATE_AUTO; + port->commit_end = cxld->id; + devm_cxl_dpa_reserve(cxled, 0, + mock_auto_region_size / cxld->interleave_ways, 0); + cxld->commit = mock_decoder_commit; + cxld->reset = mock_decoder_reset; + + WARN_ON_ONCE(!cxld_registry_new(cxld)); + /* + * Now that endpoint decoder is set up, walk up the hierarchy + * and setup the root port decoder targeting @cxlmd. + */ + dport = port->parent_dport; + root_port = dport->port; + dev = device_find_child(&root_port->dev, NULL, first_decoder); + /* + * Ancestor ports are guaranteed to be enumerated before + * @port, and all ports have at least one decoder. + */ + if (WARN_ON(!dev)) + return; + + cxlsd = to_cxl_switch_decoder(dev); + cxld = &cxlsd->cxld; + cxld->target_type = CXL_DECODER_DEVMEM; + cxld->flags = CXL_DECODER_F_ENABLE; + root_port->commit_end = 0; + cxld->interleave_ways = 1; + cxld->interleave_granularity = 4096; + cxld->target_map[0] = dport->port_id; + cxld->hpa_range = (struct range) { + .start = base, + .end = base + mock_auto_region_size - 1, + }; + cxld->commit = mock_decoder_commit; + cxld->reset = mock_decoder_reset; + + /* + * Only target_map[] is programmed above, mimicking + * firmware. On real hardware target[] is populated as + * dports enumerate, via update_decoder_targets(). The + * mock's dports are already bound by now, so fire that + * resolution explicitly here rather than stamping + * target[] directly. + */ + cxl_port_update_decoder_targets(root_port, dport); + + cxld_registry_update(cxld); + put_device(dev); +} + +static void mock_init_hdm_type3_cxled(struct cxl_endpoint_decoder *cxled, + struct cxl_port *port, + struct platform_device *pdev, + bool hb0) +{ + struct acpi_cedt_cfmws *window = mock_cfmws[0]; + struct cxl_decoder *cxld = &cxled->cxld; + struct cxl_switch_decoder *cxlsd; + struct cxl_dport *dport; + struct cxl_port *iter; + struct device *dev; + u64 base; + int i; /* Simulate missing cxl_mem.4 configuration */ if (hb0 && pdev->id == 4 && cxld->id == 0 && fail_autoassemble) { default_mock_decoder(cxld); - return false; + return; } base = window->base_hpa; @@ -1252,7 +1308,76 @@ static bool mock_init_hdm_decoder(struct cxl_decoder *cxld) cxld_registry_update(cxld); put_device(dev); } +} +/* + * Initialize a decoder during HDM enumeration. + * + * If a saved registry entry exists: + * - enabled decoders are restored from the saved programming + * - disabled decoders are initialized in a clean disabled state + * + * If no registry entry exists the decoder follows the normal mock + * initialization path, including the special auto-region setup for + * the first endpoints under host-bridge0. + * + * Returns true if decoder state was restored from the registry. In + * that case the saved decode configuration (including target mapping) + * has already been applied and the map_targets() is skipped. + */ +static bool mock_init_hdm_decoder(struct cxl_decoder *cxld) +{ + struct cxl_endpoint_decoder *cxled = NULL; + struct platform_device *pdev = NULL; + struct cxl_test_decoder *td; + struct cxl_memdev *cxlmd; + struct cxl_port *port; + bool hb0 = false; + + if (is_endpoint_decoder(&cxld->dev)) { + cxled = to_cxl_endpoint_decoder(&cxld->dev); + cxlmd = cxled_to_memdev(cxled); + WARN_ON(!dev_is_platform(cxlmd->dev.parent)); + pdev = to_platform_device(cxlmd->dev.parent); + + /* check is endpoint is attach to host-bridge0 */ + port = cxled_to_port(cxled); + do { + if (port->uport_dev == &cxl_host_bridge[0]->dev) { + hb0 = true; + break; + } + if (is_cxl_port(port->dev.parent)) + port = to_cxl_port(port->dev.parent); + else + port = NULL; + } while (port); + port = cxled_to_port(cxled); + } else { + port = to_cxl_port(cxld->dev.parent); + } + + switch (get_decoder_init_type(cxld, pdev, hb0, &td)) { + case MOCK_DECODER_INIT_SAVED: + if (WARN_ON(!td)) + return false; + return mock_decoder_handle_saved(cxld, td); + case MOCK_DECODER_INIT_DEFAULT: + /* + * The default path picks up all the decoders that are not + * endpoint. + */ + default_mock_decoder(cxld); + return false; + case MOCK_DECODER_INIT_TYPE3_AUTO: + mock_init_hdm_type3_cxled(cxled, port, pdev, hb0); + return false; + case MOCK_DECODER_INIT_TYPE2_AUTO: + mock_init_hdm_type2_cxled(cxled, port); + return false; + default: + return false; + } return false; } From 1c6b4ceafc3b994871c29340e0c1ddb0af5800e7 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Mon, 29 Jun 2026 15:11:04 -0700 Subject: [PATCH 7/8] cxl/test: Add cxl_test accelerator driver Add a type2 accelerator mock driver for the platform device that simulates a CXL type2 device. The driver exercises the same minimal API calls that a real CXL type2 driver would utilize. Tested-by: Alison Schofield Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260629221104.3891733-8-dave.jiang@intel.com Signed-off-by: Dave Jiang --- tools/testing/cxl/test/Kbuild | 2 ++ tools/testing/cxl/test/accel.c | 66 ++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 tools/testing/cxl/test/accel.c diff --git a/tools/testing/cxl/test/Kbuild b/tools/testing/cxl/test/Kbuild index c168e3c998a7..9a24ddc28488 100644 --- a/tools/testing/cxl/test/Kbuild +++ b/tools/testing/cxl/test/Kbuild @@ -5,10 +5,12 @@ obj-m += cxl_test.o obj-m += cxl_mock.o obj-m += cxl_mock_mem.o obj-m += cxl_translate.o +obj-m += cxl_mock_accel.o cxl_test-y := cxl.o cxl_test-y += hmem_test.o cxl_mock-y := mock.o cxl_mock_mem-y := mem.o +cxl_mock_accel-y := accel.o KBUILD_CFLAGS := $(filter-out -Wmissing-prototypes -Wmissing-declarations, $(KBUILD_CFLAGS)) diff --git a/tools/testing/cxl/test/accel.c b/tools/testing/cxl/test/accel.c new file mode 100644 index 000000000000..8e6f4687ca02 --- /dev/null +++ b/tools/testing/cxl/test/accel.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright(c) 2026 Intel Corporation. All rights reserved. + +#include +#include +#include +#include +#include +#include + +struct mock_cxl_accel { + struct cxl_dev_state cxlds; + struct cxl_memdev *cxlmd; +}; + +static int cxl_mock_accel_probe(struct platform_device *pdev) +{ + struct mock_cxl_accel *cxl_accel; + struct device *dev = &pdev->dev; + struct cxl_dev_state *cxlds; + struct cxl_memdev *cxlmd; + struct range mock_range; + int rc; + + cxl_accel = devm_cxl_dev_state_create(&pdev->dev, CXL_DEVTYPE_DEVMEM, + pdev->id + 1, 0, + struct mock_cxl_accel, cxlds, + false); + if (!cxl_accel) + return -ENOMEM; + + cxlds = &cxl_accel->cxlds; + cxlds->media_ready = true; + rc = cxl_set_capacity(cxlds, SZ_512M); + if (rc) + return rc; + + cxlmd = devm_cxl_probe_mem(cxlds, &mock_range); + if (IS_ERR(cxlmd)) + return PTR_ERR(cxlmd); + cxl_accel->cxlmd = cxlmd; + + dev_dbg(dev, "Probed mock accelerator with range %pra\n", &mock_range); + + return 0; +} + +static const struct platform_device_id cxl_mock_accel_ids[] = { + { .name = "cxl_type2_accel" }, + { } +}; +MODULE_DEVICE_TABLE(platform, cxl_mock_accel_ids); + +static struct platform_driver cxl_mock_accel_driver = { + .probe = cxl_mock_accel_probe, + .id_table = cxl_mock_accel_ids, + .driver = { + .name = KBUILD_MODNAME, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, +}; + +module_platform_driver(cxl_mock_accel_driver); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("cxl_test: accelerator device mock module"); +MODULE_IMPORT_NS("CXL"); From 9515af581da976911aea820175afb05be803ae8c Mon Sep 17 00:00:00 2001 From: Li Ming Date: Mon, 13 Jul 2026 14:15:31 +0800 Subject: [PATCH 8/8] cxl/test: Rework cxl_type2_mem_init() to use cxl_mock_platform_device_add() cxl_type2_mem_init() is used to set up mock CXL type2 memory device for cxl testing, it introduces a known bug fixed by the following commit: commit d90f236f8b9e ("cxl/test: Update mock dev array before calling platform_device_add()") Mock CXL devices require updating the mock device array prior to platform_device_add(), otherwise, the CXL subsystem could fail to recognize the newly added mock device. Switch to cxl_mock_platform_device_add() helper to resolve this ordering issue. Besides, this patch also includes two minor changes. 1. Preserve the original error code returned by cxl_mock_platform_device_add(), rather than unconditionally overriding it with -ENOMEM. 2. Drop redundant NULL check before platform_device_unregister(), as the function internally handles NULL pointer. Fixes: 6b2e585142e6 ("cxl/test: Add hierarchy enumeration support for type2 device") Signed-off-by: Li Ming Reviewed-by: Dave Jiang Link: https://patch.msgid.link/20260713061531.56322-1-ming.li@zohomail.com Signed-off-by: Dave Jiang --- tools/testing/cxl/test/cxl.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 8ab2ce1262f3..62bd92b3be45 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -1947,25 +1947,16 @@ static int cxl_type2_mem_init(void) pdev->dev.parent = &dport->dev; set_dev_node(&pdev->dev, i % 2); - rc = platform_device_add(pdev); - if (rc) { - rc = -ENOMEM; - platform_device_put(pdev); + rc = cxl_mock_platform_device_add(pdev, &cxl_mem[i]); + if (rc) goto err_mem; - } - cxl_mem[i] = pdev; } return 0; err_mem: - for (i = NR_CXL_TYPE2_ACCEL - 1; i >= 0; i--) { - struct platform_device *pdev = cxl_mem[i]; - - if (!pdev) - continue; - platform_device_unregister(pdev); - } + for (i = NR_CXL_TYPE2_ACCEL - 1; i >= 0; i--) + platform_device_unregister(cxl_mem[i]); return rc; }