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clk: rockchip: rk3288: Add TSP clock

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Change-Id: I02185c5ab7a1072d271cd51161f6d4b05d327673
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2018-02-01 20:36:37 +08:00 committed by Tao Huang
parent a250f09aff
commit 884b0673a7
2 changed files with 11 additions and 2 deletions
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8
drivers/clk/rockchip/clk-rk3288.c
View File

@ -534,10 +534,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0),
COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
COMPOSITE(SCLK_TSPOUT, "sclk_tspout", mux_tspout_p, 0,
RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(4), 11, GFLAGS),
COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(4), 10, GFLAGS),
@ -804,6 +804,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
GATE(SCLK_HSADC0_TSP, "clk_hsadc0_tsp", "ext_hsadc0_tsp", 0, RK3288_CLKGATE_CON(8), 9, GFLAGS),
GATE(SCLK_HSADC1_TSP, "clk_hsadc1_tsp", "ext_hsadc0_tsp", 0, RK3288_CLKGATE_CON(8), 10, GFLAGS),
GATE(SCLK_27M_TSP, "clk_27m_tsp", "ext_27m_tsp", 0, RK3288_CLKGATE_CON(8), 11, GFLAGS),
};
static const char *const rk3288_critical_clocks[] __initconst = {

5
include/dt-bindings/clock/rk3288-cru.h
View File

@ -91,6 +91,11 @@
#define SCLK_VIP_OUT 127
#define SCLK_DDRCLK 128
#define SCLK_I2S_SRC 129
#define SCLK_TSPOUT 130
#define SCLK_TSP 131
#define SCLK_HSADC0_TSP 132
#define SCLK_HSADC1_TSP 133
#define SCLK_27M_TSP 134
#define SCLK_MAC_PLL 150
#define SCLK_MAC 151