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arm64: dts: qcom: sm8250: add a link between DWC3 and QMP PHY

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The SuperSpeed signals originate from the DWC3 host controller and then
are routed through the Combo QMP PHY, where they are multiplexed with
the DisplayPort signals. Add corresponding OF graph link.

Reported-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-4-ad153c747a97@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2024-05-12 01:04:10 +03:00 committed by Bjorn Andersson
parent db67e95835
commit 8834798757
1 changed files with 22 additions and 2 deletions
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24
arch/arm64/boot/dts/qcom/sm8250.dtsi
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@ -3951,6 +3951,10 @@ port@0 {
port@1 {
reg = <1>;
usb_1_qmpphy_usb_ss_in: endpoint {
remote-endpoint = <&usb_1_dwc3_ss_out>;
};
};
port@2 {
@ -4229,8 +4233,24 @@ usb_1_dwc3: usb@a600000 {
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
port {
usb_1_dwc3_hs_out: endpoint {};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_1_dwc3_hs_out: endpoint {
};
};
port@1 {
reg = <1>;
usb_1_dwc3_ss_out: endpoint {
remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
};
};
};
};
};