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drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake

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At the moment the driver does not support AuxCCS at all due respective
modifiers being hidden from userspace.

As we are about to start enabling them, starting with Alderlake, let us
begin by limiting the ring buffer support to just that initial platform.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20260324084018.20353-4-tvrtko.ursulin@igalia.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Tvrtko Ursulin 2026-03-24 08:40:09 +00:00 committed by Rodrigo Vivi
parent 36052e56d5
commit 88139af77d
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1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/xe/xe_ring_ops.c
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@ -334,9 +334,9 @@ static bool has_aux_ccs(struct xe_device *xe)
* PVC is a special case that has no compression of either type
* (FlatCCS or AuxCCS). Also, AuxCCS is no longer used from Xe2
* onward, so any future platforms with no FlatCCS will not have
* AuxCCS either.
* AuxCCS, and we explicitly do not want to support it on MTL.
*/
if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)
if (GRAPHICS_VERx100(xe) >= 1270 || xe->info.platform == XE_PVC)
return false;
return !xe->info.has_flat_ccs;