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arm64: dts: imx95-15x15-frdm: support AONMIX MQS

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Add support for AONMIX MQS (i.e. MQS1).

Reviewed-by: Chancel Liu <chancel.liu@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2026-02-03 02:03:32 -08:00 committed by Frank Li
parent 77ae6ab965
commit 87e4207ddf
1 changed files with 73 additions and 0 deletions
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73
arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts
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@ -243,6 +243,12 @@ codec {
};
};
sound-mqs {
compatible = "audio-graph-card2";
links = <&sai1_port1>;
label = "mqs-audio";
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>;
@ -473,6 +479,21 @@ &mu7 {
status = "okay";
};
&mqs1 {
clocks = <&scmi_clk IMX95_CLK_SAI1>;
clock-names = "mclk";
pinctrl-0 = <&pinctrl_mqs1>;
pinctrl-names = "default";
status = "okay";
mqs1_port: port {
mqs1_ep: endpoint {
dai-format = "left_j";
remote-endpoint = <&sai1_port1_ep>;
};
};
};
&netc_blk_ctrl {
status = "okay";
};
@ -534,6 +555,51 @@ &pcie0 {
status = "okay";
};
&sai1 {
clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>,
<&scmi_clk IMX95_CLK_SAI1>, <&dummy>,
<&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI1>;
assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>, <3612672000>,
<393216000>, <361267200>,
<24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* leave unconnected - no RX in the context of MQS */
port@0 {
reg = <0>;
endpoint {
};
};
sai1_port1: port@1 {
reg = <1>;
mclk-fs = <512>;
sai1_port1_ep: endpoint {
dai-format = "left_j";
system-clock-direction-out;
bitclock-master;
frame-master;
remote-endpoint = <&mqs1_ep>;
};
};
};
};
&scmi_iomuxc {
pinctrl_emdio: emdiogrp {
fsl,pins = <
@ -618,6 +684,13 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
>;
};
pinctrl_mqs1: mqs1grp {
fsl,pins = <
IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x31e
IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x31e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e