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drm/xe/nvm: add support for access mode

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Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Link: https://lore.kernel.org/r/20250617145159.3803852-8-alexander.usyskin@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Alexander Usyskin 2025-06-17 17:51:57 +03:00 committed by Rodrigo Vivi
parent c28bfb107d
commit 87e1ebbafb
No known key found for this signature in database
GPG Key ID: FA625F640EEB13CA
3 changed files with 41 additions and 5 deletions
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4
drivers/gpu/drm/xe/regs/xe_gsc_regs.h
View File

@ -16,6 +16,10 @@
#define MTL_GSC_HECI1_BASE 0x00116000
#define MTL_GSC_HECI2_BASE 0x00117000
#define DG1_GSC_HECI2_BASE 0x00259000
#define PVC_GSC_HECI2_BASE 0x00285000
#define DG2_GSC_HECI2_BASE 0x00374000
#define HECI_H_CSR(base) XE_REG((base) + 0x4)
#define HECI_H_CSR_IE REG_BIT(0)
#define HECI_H_CSR_IS REG_BIT(1)

5
drivers/gpu/drm/xe/xe_heci_gsc.c
View File

@ -11,15 +11,12 @@
#include "xe_device_types.h"
#include "xe_drv.h"
#include "xe_heci_gsc.h"
#include "regs/xe_gsc_regs.h"
#include "xe_platform_types.h"
#include "xe_survivability_mode.h"
#define GSC_BAR_LENGTH 0x00000FFC
#define DG1_GSC_HECI2_BASE 0x259000
#define PVC_GSC_HECI2_BASE 0x285000
#define DG2_GSC_HECI2_BASE 0x374000
static void heci_gsc_irq_mask(struct irq_data *d)
{
/* generic irq handling */

37
drivers/gpu/drm/xe/xe_nvm.c
View File

@ -6,8 +6,11 @@
#include <linux/intel_dg_nvm_aux.h>
#include <linux/pci.h>
#include "xe_device.h"
#include "xe_device_types.h"
#include "xe_mmio.h"
#include "xe_nvm.h"
#include "regs/xe_gsc_regs.h"
#include "xe_sriov.h"
#define GEN12_GUNIT_NVM_BASE 0x00102040
@ -26,6 +29,38 @@ static void xe_nvm_release_dev(struct device *dev)
{
}
static bool xe_nvm_writable_override(struct xe_device *xe)
{
struct xe_gt *gt = xe_root_mmio_gt(xe);
bool writable_override;
resource_size_t base;
switch (xe->info.platform) {
case XE_BATTLEMAGE:
base = DG2_GSC_HECI2_BASE;
break;
case XE_PVC:
base = PVC_GSC_HECI2_BASE;
break;
case XE_DG2:
base = DG2_GSC_HECI2_BASE;
break;
case XE_DG1:
base = DG1_GSC_HECI2_BASE;
break;
default:
drm_err(&xe->drm, "Unknown platform\n");
return true;
}
writable_override =
!(xe_mmio_read32(&gt->mmio, HECI_FWSTS2(base)) &
HECI_FW_STATUS_2_NVM_ACCESS_MODE);
if (writable_override)
drm_info(&xe->drm, "NVM access overridden by jumper\n");
return writable_override;
}
int xe_nvm_init(struct xe_device *xe)
{
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
@ -50,7 +85,7 @@ int xe_nvm_init(struct xe_device *xe)
nvm = xe->nvm;
nvm->writable_override = false;
nvm->writable_override = xe_nvm_writable_override(xe);
nvm->bar.parent = &pdev->resource[0];
nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start;
nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1;