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Late devicetree changes for omaps for v5.11 merge window
Here are few more late changes that would be nice to get into v5.11: - More updates to use cpsw switchdev driver - Enable gta04 PMIC power management - Updates for dra7 for ECC support, 1.8GHz speed and keep the ldo0 regulator always on as specified in the data manual -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl/TLi8RHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXPCPQ/+O++IYDDGTicQnKFUTD+uEtzCg8viyE4k 7eJsxKybAJdivJFU2Jo0gdaqKSSb6D371pZot9H0Ps4ipO0EGuY2G+83rI41THcP 4Y2wNs9H5WjmemGVWfMJoJf4cw40pIl3BRc2zMzrSprcRZSOwACqzBHFoouXRd48 m7bX6iI8rB+GdLvy1b08fX7Iams63UsZ1rvx69LxqVDtpu7C+wX628JmtClz/hIF ldsqCiDzTHMS9I9WTwffSV0u/iPrd2iLcOnBc0zsMjhCwNs69RNReqNHHj5Lkbmv ixohmInw+ILXDgN5qZL44kJPFgrpEzVvsqvbG6SvITF+l1KPMh/tT51gIoZi9g+t KAMtWakScABYRkIf/6IBGJzssoTrLMWuSO4vw9IeGTZGe4dadGLp8nVIhBTEytX9 TZT7EjzWGWV9cwNLvHMrFyjmFlo8LXT8rZ8j6azZpW7hd2730pRCpQeuXiq3q+kz zpxj0OKBFGw1s0E5p04xVvWdGgzcevKPkOhBABnaRVocmavl1tw52fJpFD78MHF/ u3h+by1oGQxpl5aIlSjYFxcSqwazsoA46jD74C4oxMFVs/90w3jTx6UQgFviXXLg S4zOAYDn/uzr4rKFnSnW1n5CIthUO0HnZd72Lh4c8k/ymSFXfDQ7MgD1+6GGsgPS UVjMNnHqkPo= =XKaK -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.11/dt-late-signed' into omap-for-v5.12-dt Late devicetree changes for omaps for v5.11 merge window Here are few more late changes that would be nice to get into v5.11: - More updates to use cpsw switchdev driver - Enable gta04 PMIC power management - Updates for dra7 for ECC support, 1.8GHz speed and keep the ldo0 regulator always on as specified in the data manual
This commit is contained in:
commit
87ab16b644
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@ -684,28 +684,31 @@ vmmc_reg: regulator@12 {
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};
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};
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&mac {
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&mac_sw {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&cpsw_default>;
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pinctrl-1 = <&cpsw_sleep>;
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status = "okay";
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slaves = <1>;
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};
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&davinci_mdio {
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&davinci_mdio_sw {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&davinci_mdio_default>;
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pinctrl-1 = <&davinci_mdio_sleep>;
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status = "okay";
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&cpsw_emac0 {
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&cpsw_port1 {
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phy-handle = <ðphy0>;
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phy-mode = "rgmii-id";
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ti,dual-emac-pvid = <1>;
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};
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&cpsw_port2 {
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status = "disabled";
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};
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&tscadc {
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@ -596,19 +596,17 @@ vmmc_reg: regulator@12 {
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};
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};
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&mac {
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&mac_sw {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&cpsw_default>;
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pinctrl-1 = <&cpsw_sleep>;
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dual_emac = <1>;
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status = "okay";
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};
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&davinci_mdio {
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&davinci_mdio_sw {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&davinci_mdio_default>;
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pinctrl-1 = <&davinci_mdio_sleep>;
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status = "okay";
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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@ -619,16 +617,16 @@ ethphy1: ethernet-phy@1 {
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};
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};
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&cpsw_emac0 {
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&cpsw_port1 {
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phy-handle = <ðphy0>;
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phy-mode = "rgmii-id";
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dual_emac_res_vlan = <1>;
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ti,dual-emac-pvid = <1>;
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};
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&cpsw_emac1 {
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&cpsw_port2 {
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phy-handle = <ðphy1>;
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phy-mode = "rgmii-id";
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dual_emac_res_vlan = <2>;
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ti,dual-emac-pvid = <2>;
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};
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&mmc1 {
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@ -474,31 +474,29 @@ p10 {
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};
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};
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&cpsw_emac0 {
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&cpsw_port1 {
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phy-handle = <ðphy0>;
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phy-mode = "rmii";
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dual_emac_res_vlan = <1>;
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ti,dual-emac-pvid = <1>;
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};
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&cpsw_emac1 {
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&cpsw_port2 {
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phy-handle = <ðphy1>;
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phy-mode = "rmii";
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dual_emac_res_vlan = <2>;
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ti,dual-emac-pvid = <2>;
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};
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&mac {
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&mac_sw {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&cpsw_default>;
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pinctrl-1 = <&cpsw_sleep>;
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status = "okay";
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dual_emac;
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};
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&davinci_mdio {
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&davinci_mdio_sw {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&davinci_mdio_default>;
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pinctrl-1 = <&davinci_mdio_sleep>;
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status = "okay";
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reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
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reset-delay-us = <2>; /* PHY datasheet states 1uS min */
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@ -765,6 +765,55 @@ cpsw_emac1: slave@300 {
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phys = <&phy_gmii_sel 2 1>;
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};
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};
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mac_sw: switch@0 {
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compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch";
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reg = <0x0 0x4000>;
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ranges = <0 0 0x4000>;
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clocks = <&cpsw_125mhz_gclk>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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syscon = <&scm_conf>;
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status = "disabled";
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interrupts = <40 41 42 43>;
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interrupt-names = "rx_thresh", "rx", "tx", "misc";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw_port1: port@1 {
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reg = <1>;
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label = "port1";
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mac-address = [ 00 00 00 00 00 00 ];
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phys = <&phy_gmii_sel 1 1>;
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};
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cpsw_port2: port@2 {
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reg = <2>;
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label = "port2";
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mac-address = [ 00 00 00 00 00 00 ];
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phys = <&phy_gmii_sel 2 1>;
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};
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};
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davinci_mdio_sw: mdio@1000 {
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
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clocks = <&cpsw_125mhz_gclk>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <0>;
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bus_freq = <1000000>;
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reg = <0x1000 0x100>;
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};
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cpts {
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clocks = <&cpsw_cpts_rft_clk>;
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clock-names = "cpts";
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};
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};
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};
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target-module@180000 { /* 0x4a180000, ap 5 10.0 */
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@ -39,3 +39,7 @@ &mmc2 {
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&m_can0 {
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status = "disabled";
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};
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&emif1 {
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status = "okay";
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};
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@ -112,6 +112,8 @@ lp8733_ldo0_reg: ldo0 {
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regulator-name = "lp8733-ldo0";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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lp8733_ldo1_reg: ldo1 {
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@ -9,6 +9,13 @@ / {
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compatible = "ti,dra762", "ti,dra7";
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ocp {
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emif1: emif@4c000000 {
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compatible = "ti,emif-dra7xx";
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reg = <0x4c000000 0x200>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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target-module@42c01900 {
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compatible = "ti,sysc-dra7-mcan", "ti,sysc";
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ranges = <0x0 0x42c00000 0x2000>;
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@ -133,3 +140,32 @@ &mmc3 {
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/* dra76x is not affected by i887 */
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max-frequency = <96000000>;
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};
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&cpu0_opp_table {
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opp_plus@1800000000 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <1250000 950000 1250000>,
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<1250000 950000 1250000>;
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opp-supported-hw = <0xFF 0x08>;
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};
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};
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&opp_supply_mpu {
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ti,efuse-settings = <
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/* uV offset */
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1060000 0x0
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1160000 0x4
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1210000 0x8
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1250000 0xC
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>;
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};
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&abb_mpu {
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ti,abb_info = <
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/*uV ABB efuse rbb_m fbb_m vset_m*/
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1060000 0 0x0 0 0x02000000 0x01F00000
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1160000 0 0x4 0 0x02000000 0x01F00000
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1210000 0 0x8 0 0x02000000 0x01F00000
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1250000 0 0xC 0 0x02000000 0x01F00000
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>;
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};
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@ -489,8 +489,8 @@ codec {
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};
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twl_power: power {
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compatible = "ti,twl4030-power";
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ti,use_poweroff;
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compatible = "ti,twl4030-power-idle";
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ti,system-power-controller;
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};
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};
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};
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