From 85045dd45300430d258c3cc48ced9169cbbea3a6 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 8 Dec 2021 11:33:15 +0100 Subject: [PATCH 01/43] ARM: dts: stm32: remove some timer duplicate unit-address on stm32f4 series Several unused "timer" are duplicate nodes of "timers" nodes. There are two dt-schemas: - timer/st,stm32-timer.yaml: A timer is needed on STM32F4 series, on all boards, to act as clockevent. - mfd/st,stm32-timers.yaml: Timers can be used for other purpose. By default, timer5 is left enabled to be used as clockevent. Remove all other timer clockevent nodes that are currently unused and duplicated. This removes several messages: Warning (unique_unit_address): /soc/timer@.. duplicate unit-address (also used in node /soc/timers@...) Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 40 -------------------------------- 1 file changed, 40 deletions(-) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8748d5850298..f21b3227d107 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -93,14 +93,6 @@ ts_cal2: calib@22e { }; }; - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -123,14 +115,6 @@ timer@1 { }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -153,14 +137,6 @@ timer@2 { }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -212,14 +188,6 @@ timer@4 { }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -236,14 +204,6 @@ timer@5 { }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; From b380a2d1890ad26574590e80789a58886a3a7f6b Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 8 Dec 2021 11:33:16 +0100 Subject: [PATCH 02/43] ARM: dts: stm32: remove timer5 duplicate unit-address on stm32f4 series Remove the following warnings seen when building with W=1. Warning (unique_unit_address): /soc/timer@40000c00: duplicate unit-address (also used in node /soc/timers@40000c00) This approach is based on some discussions[1], to restructure the dtsi and dts files. Timer5 is enabled by default on stm32f4 series, to act as clockevent. In order to get rid of the W=1 warning, and be compliant with dt-schemas (e.g. dtbs_check): - In stm32f429.dtsi: . Keep the more complete timers5 description . Remove the most simple timer5 node that is duplicate - In each board: . adopt "st,stm32-timer" compatible for timers5, also add the interrupt . use /delete-property/ and /delete-node/ so the it matches the clockevent bindings Note: all this is done in one shot (e.g. not split) to keep clockevent functionality. [1] https://lore.kernel.org/linux-arm-kernel/Yaf4jiZIp8+ndaXs@robh.at.kernel.org/ Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32429i-eval.dts | 12 ++++++++++++ arch/arm/boot/dts/stm32f429-disco.dts | 12 ++++++++++++ arch/arm/boot/dts/stm32f429.dtsi | 7 ------- arch/arm/boot/dts/stm32f469-disco.dts | 12 ++++++++++++ 4 files changed, 36 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index cb46326a8c75..0d98aca01736 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -308,6 +308,18 @@ timer@2 { }; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 6435e099c632..3b81228d46a2 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -205,6 +205,18 @@ panel_in_rgb: endpoint { }; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index f21b3227d107..172334601faf 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -159,13 +159,6 @@ timer@3 { }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 30905ce672a0..cac3a676b4e7 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -224,6 +224,18 @@ &sdio { bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart3 { pinctrl-0 = <&usart3_pins_a>; pinctrl-names = "default"; From 7f25465e779d9eda845ec3d47151a2acd1d9e383 Mon Sep 17 00:00:00 2001 From: Reinhold Mueller Date: Thu, 9 Dec 2021 11:49:46 +0100 Subject: [PATCH 03/43] dt-binding: arm/stm32: Add emtrion hardware emSBC-Argon This patch presents the yaml patch for the emtrion GmbH Argon board series. Signed-off-by: Reinhold Mueller Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index b07720ea9611..fa0a1b84122e 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -28,6 +28,12 @@ properties: - enum: - st,stm32mp153 - st,stm32mp157 + + - description: emtrion STM32MP1 Argon based Boards + items: + - const: emtrion,stm32mp157c-emsbc-argon + - const: emtrion,stm32mp157c-emstamp-argon + - const: st,stm32mp157 - items: - enum: - st,stm32f429i-disco From 16e3e44c5b874e07dabcf2e9fd5527d810cbecdc Mon Sep 17 00:00:00 2001 From: Reinhold Mueller Date: Thu, 9 Dec 2021 11:49:47 +0100 Subject: [PATCH 04/43] ARM: dts: stm32: Add support for the emtrion emSBC-Argon This patch presents the DT patches for the emtrion GmbH Argon board series. They are available with STM32MP157 from STMicroelectronics with 512 MByte Memory. The devicetree stm32mp157c-emstamp-argon.dtsi is the common part providing the module components and the basic support for the SoC. The support for the emSBC-Argon baseboard in the developer-kit configuration is provided by the stm32mp157c-emsbc-argon.dts file. Signed-off-by: Reinhold Mueller Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 92 +++ arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts | 53 ++ .../boot/dts/stm32mp157c-emstamp-argon.dtsi | 552 ++++++++++++++++++ 4 files changed, 698 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts create mode 100644 arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 235ad559acb2..088b548d7609 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1161,6 +1161,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ + stm32mp157c-emsbc-argon.dtb \ stm32mp157c-ev1.dtb \ stm32mp157c-lxa-mc1.dtb \ stm32mp157c-odyssey.dtb diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 3b65130affec..f35230eaff92 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -338,6 +338,47 @@ pins1 { }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = , /* ETH1_CLK */ + , /* ETH1_MDC */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH1_CRS_DV */ + , /* ETH1_RXD0 */ + ; /* ETH1_RXD1 */ + bias-disable; + }; + pins4 { + pinmux = ; /* ETH1_TX_EN */ + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = , /* ETH1_MDIO */ + , /* ETH1_CRS_DV */ + , /* ETH1_CLK */ + , /* ETH1_TX_EN */ + , /* ETH1_MDC */ + , /* ETH1_RXD0 */ + , /* ETH1_RXD1 */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ @@ -927,6 +968,21 @@ pins { }; }; + pwm1_pins_b: pwm1-1 { + pins { + pinmux = ; /* TIM1_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_b: pwm1-sleep-1 { + pins { + pinmux = ; /* TIM1_CH1 */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = ; /* TIM2_CH4 */ @@ -2042,6 +2098,42 @@ pins { }; }; + usart3_pins_d: usart3-3 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_d: usart3-idle-3 { + pins1 { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_d: usart3-sleep-3 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = ; /* OTG_ID */ diff --git a/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts b/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts new file mode 100644 index 000000000000..33b3f11d24bb --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Reinhold Müller . +// + +/dts-v1/; + +#include "stm32mp157c-emstamp-argon.dtsi" + +/ { + model = "emtrion STM32MP157C emSBC-Argon Developer Board"; + compatible = "emtrion,stm32mp157c-emsbc-argon", "emtrion,stm32mp157c-emstamp-argon", + "st,stm32mp157"; + + led: gpio_leds { + compatible = "gpio-leds"; + led-2 { + label = "red"; + gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + led-3 { + label = "green"; + gpios = <&gpioe 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + }; +}; + +&dac { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi new file mode 100644 index 000000000000..33ae5e0590df --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Reinhold Müller . +// + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &usart2; + serial2 = &usart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x2000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x2000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10044000 { + compatible = "shared-dma-pool"; + reg = <0x10044000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved: gpu@dc000000 { + reg = <0xdc000000 0x4000000>; + no-map; + }; + }; + + led: gpio_leds { + compatible = "gpio-leds"; + led-0 { + label = "panic"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + led-1 { + label = "heartbeat"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_in6_pins_a>; + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <6>; + status = "disabled"; + }; + + adc2: adc@100 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + channel@12 { + reg = <12>; + label = "sense_temp"; + st,min-sample-time-ns = <9000>; + }; + channel@15 { + reg = <15>; + label = "vbat"; + st,min-sample-time-ns = <9000>; + }; + channel@16 { + reg = <16>; + label = "dac_out1"; + st,min-sample-time-ns = <9000>; + }; + channel@17 { + reg = <17>; + label = "dac_out1"; + st,min-sample-time-ns = <9000>; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "disabled"; + + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + status = "okay"; + snps,reset-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 30000 50000>; + pinctrl-0 = <ðernet0_rmii_pins_b>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; +}; + +&hash1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + regulator-always-on; + }; + + vdda: ldo6 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = ; + regulator-boot-on; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge; + }; + + vbus_usbh: pwr_sw2 { + regulator-name = "usbh_vbus"; + interrupts = ; + regulator-always-on; + regulator-boot-on; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + interrupt-names = "wdg"; + recovery; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: is25lp016d@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "disabled"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <100000>; + }; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm1_pins_b>; + pinctrl-1 = <&pwm1_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@0 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm4_pins_b>; + pinctrl-1 = <&pwm4_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers5 { + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_d>; + pinctrl-1 = <&usart3_sleep_pins_d>; + pinctrl-2 = <&usart3_idle_pins_d>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_hs_pins_a>; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; + From 2a8e68ad06ce8066eff4f955974536389f17d268 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 20 Dec 2021 21:07:33 +0100 Subject: [PATCH 05/43] ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node The stm32mp15xxaa-pinctrl.dtsi included in stm32mp15xx-dhcom-som.dtsi already sets status = "okay" in gpioc: gpio@50004000 node, drop the duplicate from stm32mp15xx-dhcom-som.dtsi . No functional change. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christoph Niedermaier Cc: Patrice Chotard Cc: Patrick Delaunay Cc: kernel@dh-electronics.com Cc: linux-stm32@st-md-mailman.stormreply.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 8c41f819f776..a10b0ba028da 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -196,7 +196,6 @@ &gpioc { "", "", "DHCOM-E", "", "", "", "", "", "", "", "", ""; - status = "okay"; }; &gpiod { From 0bb6b0f2e0e1e1351c1bebb2e954764268273c71 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:32:17 +0100 Subject: [PATCH 06/43] ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151 To align with bootloaders device tree files, and thanks to what was added in yaml file [1], the compatible property for sdmmc nodes is updated with "st,stm32-sdmmc2" string. [1] commit 552bc46484b3 ("dt-bindings: mmc: mmci: Add st,stm32-sdmmc2 compatible") Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 1cfc2f011e70..39e5ea16db88 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1059,7 +1059,7 @@ adc2: adc@100 { }; sdmmc3: mmc@48004000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; @@ -1381,7 +1381,7 @@ qspi: spi@58003000 { }; sdmmc1: mmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; @@ -1396,7 +1396,7 @@ sdmmc1: mmc@58005000 { }; sdmmc2: mmc@58007000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; From 3314f45c83c7e293920f0c96353624c0537e3777 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:32:18 +0100 Subject: [PATCH 07/43] ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp131 To align with bootloaders device tree files, and thanks to what was added in yaml file [1], the compatible property for sdmmc1 node is updated with "st,stm32-sdmmc2" string. [1] commit 552bc46484b3 ("dt-bindings: mmc: mmci: Add st,stm32-sdmmc2 compatible") Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 86126dc0d898..9b318fcd6ef0 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -122,7 +122,7 @@ syscfg: syscon@50020000 { }; sdmmc1: mmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = ; From 2434845bae3473a76c08a91fab0c6ffa6e0cac08 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:32:19 +0100 Subject: [PATCH 08/43] ARM: dts: stm32: increase SDMMC max-frequency for STM32MP13 The max-frequency limitation is due to IOs. On STM32MP13, it is 130MHz. Update the corresponding property. Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 9b318fcd6ef0..672ac9360619 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -131,7 +131,7 @@ sdmmc1: mmc@58005000 { clock-names = "apb_pclk"; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <120000000>; + max-frequency = <130000000>; status = "disabled"; }; From 864fdbe756af4ea54b6bbd7c70cb7d9bbadc33d1 Mon Sep 17 00:00:00 2001 From: Gerald Baeza Date: Wed, 12 Jan 2022 17:32:20 +0100 Subject: [PATCH 09/43] ARM: dts: stm32: update sdmmc slew-rate in stm32mp13 pinctrl SDMMC1/2 CK <= 50 MHz so slew-rate = <1> A new node sdmmc1-clk-0 is added to manage the new clock pin slew-rate. Signed-off-by: Gerald Baeza Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index 069f95f2b628..ebb83c56c350 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -7,7 +7,7 @@ &pinctrl { sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins1 { + pins { pinmux = , /* SDMMC1_D0 */ , /* SDMMC1_D1 */ , /* SDMMC1_D2 */ @@ -17,12 +17,6 @@ pins1 { drive-push-pull; bias-disable; }; - pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; }; sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { @@ -36,12 +30,6 @@ pins1 { bias-disable; }; pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { pinmux = ; /* SDMMC1_CMD */ slew-rate = <1>; drive-open-drain; @@ -49,6 +37,15 @@ pins3 { }; }; + sdmmc1_clk_pins_a: sdmmc1-clk-0 { + pins { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ From 0dbdb4862cd5ddd8c70a2499dc0f3334e81cf823 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:32:21 +0100 Subject: [PATCH 10/43] ARM: dts: stm32: update SDMMC clock slew-rate on STM32MP135F-DK board Add sdmmc1_clk_pins_a in sdmmc1 pinctrl nodes, to properly manage clock slew-rate. Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 7e96d9e36217..aae8d3512f4b 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -39,8 +39,8 @@ &iwdg2 { &sdmmc1 { pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; broken-cd; disable-wp; st,neg-edge; From ddc688c7b967509e9a4a57b6aacfdb24934bf959 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:32:22 +0100 Subject: [PATCH 11/43] ARM: dts: stm32: add sdmmc sleep pins for STM32MP13 The node sdmmc1_b4_sleep_pins_a is added in stm32mp13-pinctrl.dtsi file. Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index ebb83c56c350..c6f78eef3698 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -37,6 +37,17 @@ pins2 { }; }; + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + sdmmc1_clk_pins_a: sdmmc1-clk-0 { pins { pinmux = ; /* SDMMC1_CK */ From a6d3260019c97a06242971af9c75b3d0fbb042c6 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:32:23 +0100 Subject: [PATCH 12/43] ARM: dts: stm32: add sdmmc sleep config for STM32MP135F-DK Add sleep properties in pinctrl config for SDMMC1. Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index aae8d3512f4b..ee100d108ea2 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -38,9 +38,10 @@ &iwdg2 { }; &sdmmc1 { - pinctrl-names = "default", "opendrain"; + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; broken-cd; disable-wp; st,neg-edge; From efdf018e31e0bbd6a664ce8af5060432e13a1e31 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:33:54 +0100 Subject: [PATCH 13/43] ARM: dts: stm32: update SDMMC version for STM32MP13 On STM32MP13, the embedded SDMMC peripheral version is v2.2. Update arm,primecell-periphid for SDMMC in the SoC DT file. Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 672ac9360619..7189cba6b256 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -123,7 +123,7 @@ syscfg: syscon@50020000 { sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; + arm,primecell-periphid = <0x20253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; From a7f6433feda4465d83b450dd844ca5c61322120f Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:33:55 +0100 Subject: [PATCH 14/43] ARM: dts: stm32: add SDMMC2 in STM32MP13 DT STM32MP13 embeds 2 instances of SDMMC peripheral. Add the required information in SoC device tree file. Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 7189cba6b256..a1efb545ca3d 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -135,6 +135,20 @@ sdmmc1: mmc@58005000 { status = "disabled"; }; + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&clk_pll4_p>; + clock-names = "apb_pclk"; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; From 2f715efc19f50b28f1823478458a08666a97b38d Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Wed, 12 Jan 2022 17:33:56 +0100 Subject: [PATCH 15/43] ARM: dts: stm32: add sdmmc2 pins for STM32MP13 Those pins are used for SDIO on STM32MP135F-DK board. Signed-off-by: Yann Gautier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 51 ++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index c6f78eef3698..d2472cd8f1d0 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -57,6 +57,57 @@ pins { }; }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_clk_pins_a: sdmmc2-clk-0 { + pins { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ From b8b34b31fb5fde92278423767ac14cc8a3921445 Mon Sep 17 00:00:00 2001 From: Dillon Min Date: Tue, 26 Oct 2021 15:11:15 +0800 Subject: [PATCH 16/43] ARM: dts: stm32: Add DMA2D support for STM32F429 series soc Add DMA2D for STM32F429 series soc. Signed-off-by: Dillon Min Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 172334601faf..c31ceb821231 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -712,6 +712,16 @@ mac: ethernet@40028000 { status = "disabled"; }; + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + status = "disabled"; + }; + usbotg_hs: usb@40040000 { compatible = "snps,dwc2"; reg = <0x40040000 0x40000>; From 6ced294e9f848e04a96ffbf26e729883f85c310f Mon Sep 17 00:00:00 2001 From: Dillon Min Date: Tue, 26 Oct 2021 15:11:16 +0800 Subject: [PATCH 17/43] ARM: dts: stm32: Enable DMA2D on STM32F469-DISCO board Enable DMA2D on STM32F469-DISCO board. Signed-off-by: Dillon Min Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f469-disco.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index cac3a676b4e7..5a0daf8e8b11 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -132,6 +132,10 @@ &clk_hse { clock-frequency = <8000000>; }; +&dma2d { + status = "okay"; +}; + &dsi { #address-cells = <1>; #size-cells = <0>; From ee2aacb6f3a901a95b1dd68964b69c92cdbbf213 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Mon, 24 Jan 2022 16:35:25 +0100 Subject: [PATCH 18/43] ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15 Replace sai2a-2 node name by sai2a-sleep-2, to avoid name duplication. Fixes: 1a9a9d226f0f ("ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15") Signed-off-by: Olivier Moysan Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index f35230eaff92..f0d66d8c6e3b 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1246,7 +1246,7 @@ pins { }; }; - sai2a_sleep_pins_c: sai2a-2 { + sai2a_sleep_pins_c: sai2a-sleep-2 { pins { pinmux = , /* SAI2_SCK_A */ , /* SAI2_SD_A */ From 54ceceeaee479c3f08ed5a5d0af0d10769567ca5 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 1 Feb 2022 17:05:05 +0100 Subject: [PATCH 19/43] ARM: dts: stm32: add DMA1, DMA2 and DMAMUX1 on STM32MP13x SoC family DMA1 and DMA2 on STM32MP13x SoCs are the same than on STM32MP15x SoCs: they offer up to 8 channels and request lines are routed through DMAMUX1. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 44 +++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index a1efb545ca3d..97aa173cf99f 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -115,6 +115,50 @@ uart4: serial@40010000 { status = "disabled"; }; + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clk_pclk4>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clk_pclk4>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + clocks = <&clk_pclk4>; + #dma-cells = <3>; + dma-masters = <&dma1 &dma2>; + dma-requests = <128>; + dma-channels = <16>; + }; + syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; From 26c1d8c7fe90d80f6c85bbd8c59ce7bebaf33b00 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Mon, 7 Feb 2022 12:52:12 +0100 Subject: [PATCH 20/43] ARM: dts: stm32: add MDMA on STM32MP13x SoC family MDMA on STM32MP13x SoCs is the same than on STM32MP15x SoCs: it offers up to 32 channels and supports 48 requests. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 97aa173cf99f..01f53ffe7837 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -165,6 +165,16 @@ syscfg: syscon@50020000 { clocks = <&clk_pclk3>; }; + mdma: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&clk_pclk4>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; + }; + sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x20253180>; From 1deab7ed164fc4df348dd0401d34d2ff5b48edd5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 11 Jan 2022 03:48:02 +0100 Subject: [PATCH 21/43] ARM: dts: stm32: Add CM4 reserved memory, rproc and IPCC on DHCOR SoM Add reserved memory nodes for CortexM4 on the STM32MP1 DHCOR SoM, enable rproc to control the CM4 and IPCC mailbox to interact with it. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 44ecc4708587..6336c3ca0f0e 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -19,6 +19,48 @@ memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x40000000>; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; }; &crc1 { @@ -179,11 +221,25 @@ eeprom@53 { }; }; +&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; }; +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + &pwr_regulators { vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; From 7a5faaee0d2e6f60897eed43366d8b541ea7882c Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 3 Feb 2022 02:59:58 +0100 Subject: [PATCH 22/43] ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on stm32mp157 Link between GIC and exti line is now done inside EXTI driver. So in order to be wake up source exti irqchip has to be used. Signed-off-by: Alexandre Torgue Cc: Alexandre Torgue Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 39e5ea16db88..f26697330c0c 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1560,7 +1560,7 @@ rtc: rtc@5c004000 { reg = <0x5c004000 0x400>; clocks = <&rcc RTCAPB>, <&rcc RTC>; clock-names = "pclk", "rtc_ck"; - interrupts = ; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; From 0f18f728ba6281fa63fde978fe8efb11d76aaef0 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:10:59 +0100 Subject: [PATCH 23/43] ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151 Add DMA configuration in stm32mp15x uart nodes by selecting dma direct mode and alternate REQ/ACK dma protocol for uart. DMA direct mode allows to bypass DMA FIFO. Each DMA request immediately initiates a transfer from/to the memory. This allows USART to get data transferred, even when the transfer ends before the DMA FIFO completion. Default REQ/ACK DMA protocol consists in maintaining ACK signal up to the removal of REQuest and the transfer completion. In case of alternative REQ/ACK protocol, ACK de-assertion does not wait the removal of the REQuest, but only the transfer completion. Due to a possible DMA stream lock when transferring data to/from STM32 USART/UART, select this alternative protocol in STM32 USART/UART nodes. Signed-off-by: Valentin Caron Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index f26697330c0c..2171e7a97e92 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -455,6 +455,9 @@ usart2: serial@4000e000 { interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART2_K>; wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -464,6 +467,9 @@ usart3: serial@4000f000 { interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART3_K>; wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -473,6 +479,9 @@ uart4: serial@40010000 { interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -482,6 +491,9 @@ uart5: serial@40011000 { interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART5_K>; wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -588,6 +600,9 @@ uart7: serial@40018000 { interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART7_K>; wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -597,6 +612,9 @@ uart8: serial@40019000 { interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART8_K>; wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -678,6 +696,9 @@ usart6: serial@44003000 { interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART6_K>; wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; From 8201f5f5fd2cec4b0fff2e2c7a112126bbc9400a Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:00 +0100 Subject: [PATCH 24/43] ARM: dts: stm32: keep uart4 behavior on stm32mp157c-ed1 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157c-ed1 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 46b471d09c50..b1eb688a278a 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -384,6 +384,8 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From 76594563fac74d6fbc247e9949cca54555e51231 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:01 +0100 Subject: [PATCH 25/43] ARM: dts: stm32: keep uart4 and uart7 behavior on stm32mp15xx-dkx DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp15xx-dkx board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also uart7 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 6caeb448c190..333c2af97130 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -650,6 +650,8 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -658,6 +660,8 @@ &uart7 { pinctrl-0 = <&uart7_pins_c>; pinctrl-1 = <&uart7_sleep_pins_c>; pinctrl-2 = <&uart7_idle_pins_c>; + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; }; From 97f44495f80e4f0d975d5bf1903c7917f601b381 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:02 +0100 Subject: [PATCH 26/43] ARM: dts: stm32: keep uart4 behavior on icore-stm32mp1-ctouch2 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in icore-stm32mp1-ctouch2 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts index d3058a036c74..1f75f1d45181 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -43,5 +43,7 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From 2fd0c0fe7a49467ae7af9e9dfbc19ed081c4e21a Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:03 +0100 Subject: [PATCH 27/43] ARM: dts: stm32: keep uart4 behavior on icore-stm32mp1-edimm2.2 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in icore-stm32mp1-edimm2.2 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index a797eaa917b7..ba92d7d8ed00 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -128,5 +128,7 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From 49bc295c6a5321f4856bc7cf45c68dbe87e76bc9 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:04 +0100 Subject: [PATCH 28/43] ARM: dts: stm32: keep uart4 behavior on stm32mp157a-iot-box DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157a-iot-box board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-iot-box.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/stm32mp157a-iot-box.dts index 70f394b4d3c0..6a5a4af25bd9 100644 --- a/arch/arm/boot/dts/stm32mp157a-iot-box.dts +++ b/arch/arm/boot/dts/stm32mp157a-iot-box.dts @@ -58,6 +58,8 @@ &uart4 { /delete-property/st,hw-flow-ctrl; cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; bluetooth { From ab0e8febe59feefb5e190a28c805277735fc1bda Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:05 +0100 Subject: [PATCH 29/43] ARM: dts: stm32: keep uart nodes behavior on stm32mp1-microdev2.0-of7 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp1-microdev2.0-of7 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also uart8 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- .../dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 5670b23812a2..fae656edd820 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -143,6 +143,8 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -150,5 +152,7 @@ &uart4 { &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From 9e9388e2ff6726bc65b539fc13d997103aa2aef4 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:06 +0100 Subject: [PATCH 30/43] ARM: dts: stm32: keep uart nodes behavior on stm32mp1-microdev2.0 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp1-microdev2.0 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also uart8 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- .../boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index 7a75868164dc..b9d0d3d6ad15 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -44,6 +44,8 @@ &uart4 { pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -51,5 +53,7 @@ &uart4 { &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From ee41561d9c96d9b931a64bf0d56ac126d4f718b1 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:07 +0100 Subject: [PATCH 31/43] ARM: dts: stm32: keep uart nodes behavior on stm32mp157a-stinger96 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157a-stinger96 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also usart2 and uart7 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi index a4b14ef3caee..3a36f7fe0a2c 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -288,6 +288,8 @@ &usart2 { pinctrl-0 = <&usart2_pins_b>; pinctrl-1 = <&usart2_sleep_pins_b>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -296,6 +298,8 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_c>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -303,6 +307,8 @@ &uart4 { &uart7 { pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From aed569aaf1ca7a88a344308152d12ecf16b9e85f Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:08 +0100 Subject: [PATCH 32/43] ARM: dts: stm32: keep uart4 behavior on stm32mp157c-lxa-mc1 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157c-lxa-mc1 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray Reviewed-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 1e9bf7eea0f1..e8d2ec41d537 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -248,5 +248,7 @@ leds_pwm: pwm { &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From d8268564a3b7fc4b63a4c8790867baba91e50e8e Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:09 +0100 Subject: [PATCH 33/43] ARM: dts: stm32: keep uart4 behavior on stm32mp157c-odyssey DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp157c-odyssey board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-odyssey.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts index 554f5d3bcdc3..ed66d25b8bf3 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -81,6 +81,8 @@ &sdmmc1 { &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From 97b37fb0752a77ad5db4da26b111f4b720877b6b Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:10 +0100 Subject: [PATCH 34/43] ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-drc02 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete usart3 and uart8 nodes DMA property in stm32mp15xx-dhcom-drc02 board device tree to keep current behavior. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi index 4b10b013ffd5..35b1034aa3cf 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -131,6 +131,8 @@ &spi1 { &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -144,6 +146,8 @@ &uart8 { /* RS485 */ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From 89104f45a3b998b870fda0c2d14e0bbea9e7d591 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:11 +0100 Subject: [PATCH 35/43] ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-pdk2 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete usart3 and uart8 DMA property in stm32mp15xx-dhcom-pdk2 board device tree to keep current behavior. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index fbf3826933e4..5f586f024060 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -287,6 +287,8 @@ timer@1 { &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -294,6 +296,8 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From b1bcd81718fb256b005cfad3c54398a13d35fc06 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:12 +0100 Subject: [PATCH 36/43] ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-picoitx DMA configuration is added to uart nodes in stm32mp15x device tree. Delete usart3 and uart8 nodes DMA property in stm32mp15xx-dhcom-picoitx board device tree to keep current behavior. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi index ba816ef8b9b2..abc595350e71 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi @@ -105,12 +105,16 @@ &ksz8851 { &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From 9269f28b7df5c8067b6e3df387dcf4eaf8b6c211 Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:13 +0100 Subject: [PATCH 37/43] ARM: dts: stm32: keep uart4 behavior on stm32mp15xx-dhcom-som DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp15xx-dhcom-som board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index a10b0ba028da..83e2c87713f8 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -520,5 +520,7 @@ &sdmmc3 { &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; From 2a8092a5a60da82c32ed78da3a980a78bb70f56c Mon Sep 17 00:00:00 2001 From: Erwan Le Ray Date: Thu, 3 Feb 2022 18:11:14 +0100 Subject: [PATCH 38/43] ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcor-avenger96 DMA configuration is added to uart nodes in stm32mp15x device tree. Delete uart4 DMA property in stm32mp15xx-dhcor-avenger96 board device tree to keep console in irq mode, as DMA support for console has been removed from the driver by commit e359b4411c28 ("serial: stm32: fix threaded interrupt handling"). Delete also usart2 and uart7 DMA property to keep current behavior. Signed-off-by: Erwan Le Ray Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 6885948f3024..61e17f44ce81 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -376,6 +376,8 @@ &uart4 { label = "LS-UART1"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -385,6 +387,8 @@ &uart7 { pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -394,6 +398,8 @@ &usart2 { pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; bluetooth { From f03b9808e6e4e8cf9eb7268575cb99b64a6973c5 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Wed, 2 Feb 2022 15:00:05 +0100 Subject: [PATCH 39/43] ARM: dts: stm32: Enable EXTI on stm32mp13 As EXTI/GIC mapping has changed between STM32MP15 and STM32MP13, a new compatible is needed to choose mp13 mapping table in stm32-exti driver. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 01f53ffe7837..262de4eeb4ed 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -159,6 +159,13 @@ dmamux1: dma-router@48002000 { dma-channels = <16>; }; + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; From e6bc0d6ac6d69d3d9a7d43bce37ed4104542ba3c Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 9 Feb 2022 11:48:48 +0100 Subject: [PATCH 40/43] ARM: dts: stm32: remove some timer duplicate unit-address on stm32f7 series Several unused "timer" are duplicate nodes of "timers" nodes. There are two dt-schemas: - timer/st,stm32-timer.yaml: A timer is needed on STM32F7 series, on all boards, to act as clockevent. - mfd/st,stm32-timers.yaml: Timers can be used for other purpose. By default, timer5 is left enabled to be used as clockevent. Remove all other timer clockevent nodes that are currently unused and duplicated. This removes several messages: Warning (unique_unit_address): /soc/timer@.. duplicate unit-address (also used in node /soc/timers@...) Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f746.dtsi | 40 -------------------------------- 1 file changed, 40 deletions(-) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 014b416f57e6..a4f5c6a66e08 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -75,14 +75,6 @@ clk_i2s_ckin: clk-i2s-ckin { }; soc { - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -105,14 +97,6 @@ timer@1 { }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -135,14 +119,6 @@ timer@2 { }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +170,6 @@ timer@4 { }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +186,6 @@ timer@5 { }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; From b814f7544a8f669c8c64abccb3e384dbd868a0aa Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 9 Feb 2022 11:48:49 +0100 Subject: [PATCH 41/43] ARM: dts: stm32: remove timer5 duplicate unit-address on stm32f7 series Remove the following warnings seen when building with W=1. Warning (unique_unit_address): /soc/timer@40000c00: duplicate unit-address (also used in node /soc/timers@40000c00) This approach is based on some discussions[1], to restructure the dtsi and dts files. Timer5 is enabled by default on stm32f7 series, to act as clockevent. In order to get rid of the W=1 warning, and be compliant with dt-schemas (e.g. dtbs_check): - In stm32f746.dtsi: . Keep the more complete timers5 description . Remove the most simple timer5 node that is duplicate - In each board: . adopt "st,stm32-timer" compatible for timers5, also add the interrupt . use /delete-property/ and /delete-node/ so the it matches the clockevent bindings Note: all this is done in one shot (e.g. not split) to keep clockevent functionality. [1] https://lore.kernel.org/linux-arm-kernel/Yaf4jiZIp8+ndaXs@robh.at.kernel.org/ Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32746g-eval.dts | 12 ++++++++++++ arch/arm/boot/dts/stm32f746-disco.dts | 12 ++++++++++++ arch/arm/boot/dts/stm32f746.dtsi | 7 ------- arch/arm/boot/dts/stm32f769-disco.dts | 12 ++++++++++++ 4 files changed, 36 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 327613fd9666..a293e65141c6 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -194,6 +194,18 @@ &sdio1 { bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts index 569d23cc61e5..c11616ed5fc6 100644 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -109,6 +109,18 @@ &sdio1 { bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index a4f5c6a66e08..dc868e6da40e 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -141,13 +141,6 @@ timer@3 { }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index be943b701980..b038d0ed39e8 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -137,6 +137,18 @@ &sdio2 { bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; From bf5f07e70687468c9d56f1e9e1840416413b8003 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Mon, 21 Feb 2022 14:10:38 +0100 Subject: [PATCH 42/43] ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp13 Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP13 is a single core A7. Signed-off-by: Alexandre Torgue Acked-by: Marc Zyngier --- arch/arm/boot/dts/stm32mp131.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 262de4eeb4ed..1708c79b5254 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -92,10 +92,10 @@ psci { timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&intc>; always-on; }; From cb4b2d26c78a1707499bf60768e463032a221e3a Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Mon, 21 Feb 2022 14:15:08 +0100 Subject: [PATCH 43/43] ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15 Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP151 is a single A7. STM32MP153/157 is a dual A7. Signed-off-by: Alexandre Torgue Acked-by: Marc Zyngier --- arch/arm/boot/dts/stm32mp151.dtsi | 8 ++++---- arch/arm/boot/dts/stm32mp153.dtsi | 7 +++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 2171e7a97e92..f9aa9af31efd 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -45,10 +45,10 @@ intc: interrupt-controller@a0021000 { timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&intc>; }; diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi index 1c1889b194cf..486084e0b80b 100644 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -22,6 +22,13 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; + timer { + interrupts = , + , + , + ; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can";