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drm/i915/pps: Spell out the eDP spec power sequencing delays a bit more clearly

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We determine the "spec" eDP power sequencing delays
by referencing some max values from the eDP spec.
Write out each number from the spec explicitly instead
of precomputing the final number (that's the job of
the computer). Makes it a bit easier to see what the
supposed spec defined numbers actually are.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241106215859.25446-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2024-11-06 23:58:56 +02:00
parent ccae47c64b
commit 87545d7584
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/i915/display/intel_pps.c
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@ -1512,11 +1512,11 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp,
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
* our hw here, which are all in 100usec. */
spec->power_up = 210 * 10; /* T1+T3 */
spec->power_up = (10 + 200) * 10; /* T1+T3 */
spec->backlight_on = 50 * 10; /* no limit for T8, use T7 instead */
spec->backlight_off = 50 * 10; /* no limit for T9, make it symmetric with T8 */
spec->power_down = 500 * 10; /* T10 */
spec->power_cycle = 510 * 10; /* T11+T12 */
spec->power_cycle = (10 + 500) * 10; /* T11+T12 */
intel_pps_dump_state(intel_dp, "spec", spec);
}