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arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588
The Rockchip RK3588 features two MIPI CSI-2 DPHYs. Add the device tree nodes for them. Signed-off-by: Michael Riesch <michael.riesch@collabora.com> Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-7-a4f340a7f0cf@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -621,6 +621,16 @@ php_grf: syscon@fd5b0000 {
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reg = <0x0 0xfd5b0000 0x0 0x1000>;
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};
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csidphy0_grf: syscon@fd5b4000 {
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compatible = "rockchip,rk3588-csidphy-grf", "syscon";
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reg = <0x0 0xfd5b4000 0x0 0x1000>;
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};
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csidphy1_grf: syscon@fd5b5000 {
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compatible = "rockchip,rk3588-csidphy-grf", "syscon";
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reg = <0x0 0xfd5b5000 0x0 0x1000>;
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};
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pipe_phy0_grf: syscon@fd5bc000 {
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compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
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reg = <0x0 0xfd5bc000 0x0 0x100>;
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@ -3176,6 +3186,30 @@ mipidcphy1: phy@fedb0000 {
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status = "disabled";
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};
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csi_dphy0: phy@fedc0000 {
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compatible = "rockchip,rk3588-csi-dphy";
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reg = <0x0 0xfedc0000 0x0 0x8000>;
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clocks = <&cru PCLK_CSIPHY0>;
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clock-names = "pclk";
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#phy-cells = <0>;
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resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
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reset-names = "apb", "phy";
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rockchip,grf = <&csidphy0_grf>;
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status = "disabled";
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};
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csi_dphy1: phy@fedc8000 {
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compatible = "rockchip,rk3588-csi-dphy";
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reg = <0x0 0xfedc8000 0x0 0x8000>;
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clocks = <&cru PCLK_CSIPHY1>;
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clock-names = "pclk";
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#phy-cells = <0>;
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resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>;
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reset-names = "apb", "phy";
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rockchip,grf = <&csidphy1_grf>;
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status = "disabled";
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};
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combphy0_ps: phy@fee00000 {
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compatible = "rockchip,rk3588-naneng-combphy";
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reg = <0x0 0xfee00000 0x0 0x100>;
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