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perf vendor events: Update SapphireRapids events

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Update events from v1.25 to v1.28.

Bring in the event updates v1.28:
990bfdff27
b7b4d7f18c

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Link: https://lore.kernel.org/r/20250630163101.1920170-13-irogers@google.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Ian Rogers 2025-06-30 09:30:57 -07:00 committed by Namhyung Kim
parent 1f9e24e4df
commit 8704418511
4 changed files with 34 additions and 2 deletions
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2
tools/perf/pmu-events/arch/x86/mapfile.csv
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@ -29,7 +29,7 @@ GenuineIntel-6-2E,v4,nehalemex,core
GenuineIntel-6-CC,v1.00,pantherlake,core
GenuineIntel-6-A7,v1.04,rocketlake,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-8F,v1.25,sapphirerapids,core
GenuineIntel-6-8F,v1.28,sapphirerapids,core
GenuineIntel-6-AF,v1.09,sierraforest,core
GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core

1 Family-model Version Filename EventType
29 GenuineIntel-6-CC v1.00 pantherlake core
30 GenuineIntel-6-A7 v1.04 rocketlake core
31 GenuineIntel-6-2A v19 sandybridge core
32 GenuineIntel-6-8F v1.25 v1.28 sapphirerapids core
33 GenuineIntel-6-AF v1.09 sierraforest core
34 GenuineIntel-6-(37|4A|4C|4D|5A) v15 silvermont core
35 GenuineIntel-6-(4E|5E|8E|9E|A5|A6) v59 skylake core

2
tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json
View File

@ -684,7 +684,7 @@
"Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
"PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
"SampleAfterValue": "100003",
"UMask": "0x1"
},

12
tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json
View File

@ -1901,6 +1901,18 @@
"UMask": "0x4",
"Unit": "IIO"
},
{
"BriefDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED",
"Experimental": "1",
"FCMask": "0x01",
"PerPkg": "1",
"PortMask": "0x00FF",
"UMask": "0x4",
"Unit": "IIO"
},
{
"BriefDescription": "ITC address map 1",
"Counter": "0,1,2,3",

20
tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json
View File

@ -2145,6 +2145,16 @@
"UMask": "0x1",
"Unit": "MCHBM"
},
{
"BriefDescription": "ECC Correctable Errors",
"Counter": "0,1,2,3",
"EventCode": "0x09",
"EventName": "UNC_MCHBM_ECC_CORRECTABLE_ERRORS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ECC Correctable Errors. Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
"Unit": "MCHBM"
},
{
"BriefDescription": "HBM Precharge All Commands",
"Counter": "0,1,2,3",
@ -2759,6 +2769,16 @@
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "ECC Correctable Errors",
"Counter": "0,1,2,3",
"EventCode": "0x09",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ECC Correctable Errors : Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
"Unit": "iMC"
},
{
"BriefDescription": "IMC Clockticks at HCLK frequency",
"Counter": "0,1,2,3",