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drm/amd/display: Refactor DML21 Initialization and Configuration
[Why & How] - Consolidated the initialization of DML21 parameters into a single function `dml21_populate_dml_init_params` to streamline the process and improve code readability. - Updated the function signatures in the header files to reflect changes in parameter passing for DML context. - Removed redundant debug option handling and integrated it into the new configuration population function. - Adjusted the DML21 initialization logic in the wrapper to accommodate the new structure, ensuring compatibility with different DCN versions. - Enhanced the handling of clock parameters and bounding box configurations from various sources, including hardware defaults and software policies. - Improved the clarity of the code by renaming functions and variables for better understanding of their purposes. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wenjing Liu
Alex Deucher
parent
8ebfc4d25a
commit
86fa0b9830
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@ -2,7 +2,6 @@
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//
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// Copyright 2024 Advanced Micro Devices, Inc.
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#include "dml21_wrapper.h"
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#include "dml2_core_dcn4_calcs.h"
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#include "dml2_internal_shared_types.h"
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@ -11,286 +10,263 @@
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#include "dml21_translation_helper.h"
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#include "bounding_boxes/dcn4_soc_bb.h"
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static void dml21_apply_dmub_bb_params(struct dml2_soc_bb *soc_bb, const void *dmub_bb_params, const struct dc *in_dc)
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static void dml21_populate_pmo_options(struct dml2_pmo_options *pmo_options,
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const struct dc *in_dc,
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const struct dml2_configuration_options *config)
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{
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bool disable_fams2 = !in_dc->debug.fams2_config.bits.enable;
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/* ODM options */
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pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm;
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pmo_options->disable_dyn_odm_for_multi_stream = true;
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pmo_options->disable_dyn_odm_for_stream_with_svp = true;
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pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1);
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/* NOTE: DRR and SubVP Require FAMS2 */
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pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) ||
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in_dc->debug.force_disable_subvp ||
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disable_fams2;
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pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||
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disable_fams2;
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pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) ||
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disable_fams2;
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pmo_options->disable_fams2 = disable_fams2;
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pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE ||
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in_dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY;
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pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE;
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}
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/*
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* Populate dml_init based on default static values in soc bb. The default
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* values are for reference and support at least minimal operation of current
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* SoC and DCN hardware. The values could be modifed by subsequent override
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* functions to reflect our true hardware capability.
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*/
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static void populate_default_dml_init_params(struct dml2_initialize_instance_in_out *dml_init,
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const struct dml2_configuration_options *config,
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const struct dc *in_dc)
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{
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switch (in_dc->ctx->dce_version) {
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case DCN_VERSION_4_01:
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default:
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dml_init->options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp;
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dml21_populate_pmo_options(&dml_init->options.pmo_options, in_dc, config);
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dml_init->soc_bb = dml2_socbb_dcn401;
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dml_init->soc_bb.qos_parameters = dml_dcn4_variant_a_soc_qos_params;
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dml_init->ip_caps = dml2_dcn401_max_ip_caps;
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break;
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}
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}
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static void dml21_init_socbb_params(struct dml2_initialize_instance_in_out *dml_init,
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const struct dml2_configuration_options *config,
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const struct dc *in_dc)
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{
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const struct dml2_soc_bb *soc_bb;
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const struct dml2_soc_qos_parameters *qos_params;
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switch (in_dc->ctx->dce_version) {
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case DCN_VERSION_4_01:
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default:
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soc_bb = &dml2_socbb_dcn401;
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qos_params = &dml_dcn4_variant_a_soc_qos_params;
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memset(dml_init, 0, sizeof(*dml_init));
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DC_ERR("unsupported dcn version for DML21!");
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return;
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}
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/* patch soc bb */
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memcpy(&dml_init->soc_bb, soc_bb, sizeof(struct dml2_soc_bb));
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if (config->bb_from_dmub)
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dml21_apply_dmub_bb_params(&dml_init->soc_bb, config->bb_from_dmub, in_dc);
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/* patch qos params */
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memcpy(&dml_init->soc_bb.qos_parameters, qos_params, sizeof(struct dml2_soc_qos_parameters));
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}
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static void dml21_external_socbb_params(struct dml2_initialize_instance_in_out *dml_init,
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const struct dml2_configuration_options *config)
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{
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memcpy(&dml_init->soc_bb, &config->external_socbb_ip_params->soc_bb, sizeof(struct dml2_soc_bb));
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}
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static void dml21_external_ip_params(struct dml2_initialize_instance_in_out *dml_init,
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const struct dml2_configuration_options *config)
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{
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memcpy(&dml_init->ip_caps, &config->external_socbb_ip_params->ip_params, sizeof(struct dml2_ip_capabilities));
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}
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static void dml21_init_ip_params(struct dml2_initialize_instance_in_out *dml_init,
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static void override_dml_init_with_values_from_hardware_default(struct dml2_initialize_instance_in_out *dml_init,
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const struct dml2_configuration_options *config,
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const struct dc *in_dc)
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{
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const struct dml2_ip_capabilities *ip_caps;
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switch (in_dc->ctx->dce_version) {
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case DCN_VERSION_4_01:
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default:
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ip_caps = &dml2_dcn401_max_ip_caps;
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}
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memcpy(&dml_init->ip_caps, ip_caps, sizeof(struct dml2_ip_capabilities));
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dml_init->soc_bb.dchub_refclk_mhz = in_dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
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dml_init->soc_bb.dprefclk_mhz = in_dc->clk_mgr->dprefclk_khz / 1000;
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dml_init->soc_bb.dispclk_dppclk_vco_speed_mhz = in_dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
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}
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void dml21_initialize_soc_bb_params(struct dml2_initialize_instance_in_out *dml_init,
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/*
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* SMU stands for System Management Unit. It is a power management processor.
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* It owns the initialization of dc's clock table and programming of clock values
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* based on dc's requests.
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* Our clock values in base soc bb is a dummy placeholder. The real clock values
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* are retrieved from SMU firmware to dc clock table at runtime.
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* This function overrides our dummy placeholder values with real values in dc
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* clock table.
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*/
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static void override_dml_init_with_values_from_smu(
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struct dml2_initialize_instance_in_out *dml_init,
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const struct dml2_configuration_options *config,
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const struct dc *in_dc)
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{
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if (config->use_native_soc_bb_construction)
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dml21_init_socbb_params(dml_init, config, in_dc);
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else
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dml21_external_socbb_params(dml_init, config);
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}
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void dml21_initialize_ip_params(struct dml2_initialize_instance_in_out *dml_init,
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const struct dml2_configuration_options *config,
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const struct dc *in_dc)
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{
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if (config->use_native_soc_bb_construction)
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dml21_init_ip_params(dml_init, config, in_dc);
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else
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dml21_external_ip_params(dml_init, config);
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}
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void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_init,
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const struct dml2_configuration_options *config, const struct dc *in_dc)
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{
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int i;
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const struct clk_bw_params *dc_bw_params = in_dc->clk_mgr->bw_params;
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const struct clk_limit_table *dc_clk_table = &dc_bw_params->clk_table;
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struct dml2_soc_bb *dml_soc_bb = &dml_init->soc_bb;
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struct dml2_soc_state_table *dml_clk_table = &dml_soc_bb->clk_table;
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struct dml2_soc_state_table *dml_clk_table = &dml_init->soc_bb.clk_table;
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/* override clocks if smu is present */
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if (in_dc->clk_mgr->funcs->is_smu_present && in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) {
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/* dcfclk */
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if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
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dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
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for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
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if (i < dml_clk_table->dcfclk.num_clk_values) {
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if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz &&
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dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) {
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if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) {
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dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000;
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dml_clk_table->dcfclk.num_clk_values = i + 1;
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} else {
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dml_clk_table->dcfclk.clk_values_khz[i] = 0;
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dml_clk_table->dcfclk.num_clk_values = i;
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}
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if (!in_dc->clk_mgr->funcs->is_smu_present ||
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!in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr))
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/* skip if smu is not present */
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return;
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/* dcfclk */
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if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
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dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
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for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
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if (i < dml_clk_table->dcfclk.num_clk_values) {
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if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz &&
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dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) {
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if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) {
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dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000;
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dml_clk_table->dcfclk.num_clk_values = i + 1;
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} else {
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dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000;
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dml_clk_table->dcfclk.clk_values_khz[i] = 0;
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dml_clk_table->dcfclk.num_clk_values = i;
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}
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} else {
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dml_clk_table->dcfclk.clk_values_khz[i] = 0;
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dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000;
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}
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} else {
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dml_clk_table->dcfclk.clk_values_khz[i] = 0;
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}
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}
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/* fclk */
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if (dc_clk_table->num_entries_per_clk.num_fclk_levels) {
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dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels;
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for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
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if (i < dml_clk_table->fclk.num_clk_values) {
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if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz &&
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dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) {
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if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) {
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dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000;
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dml_clk_table->fclk.num_clk_values = i + 1;
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} else {
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dml_clk_table->fclk.clk_values_khz[i] = 0;
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dml_clk_table->fclk.num_clk_values = i;
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}
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} else {
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dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000;
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}
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} else {
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dml_clk_table->fclk.clk_values_khz[i] = 0;
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}
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}
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}
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/* uclk */
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if (dc_clk_table->num_entries_per_clk.num_memclk_levels) {
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dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels;
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for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
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if (i < dml_clk_table->uclk.num_clk_values) {
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if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz &&
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dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) {
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if (i == 0 || dc_clk_table->entries[i-1].memclk_mhz < dc_bw_params->dc_mode_limit.memclk_mhz) {
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dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000;
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dml_clk_table->uclk.num_clk_values = i + 1;
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} else {
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dml_clk_table->uclk.clk_values_khz[i] = 0;
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dml_clk_table->uclk.num_clk_values = i;
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}
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} else {
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dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000;
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}
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} else {
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dml_clk_table->uclk.clk_values_khz[i] = 0;
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}
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}
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}
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/* dispclk */
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if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) {
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dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels;
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for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
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if (i < dml_clk_table->dispclk.num_clk_values) {
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if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz &&
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dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) {
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if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) {
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dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000;
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dml_clk_table->dispclk.num_clk_values = i + 1;
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} else {
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dml_clk_table->dispclk.clk_values_khz[i] = 0;
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dml_clk_table->dispclk.num_clk_values = i;
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}
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} else {
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dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000;
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}
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} else {
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dml_clk_table->dispclk.clk_values_khz[i] = 0;
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}
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}
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}
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/* dppclk */
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if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) {
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dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels;
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for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
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if (i < dml_clk_table->dppclk.num_clk_values) {
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if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz &&
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dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) {
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if (i == 0 || dc_clk_table->entries[i-1].dppclk_mhz < dc_bw_params->dc_mode_limit.dppclk_mhz) {
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dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000;
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dml_clk_table->dppclk.num_clk_values = i + 1;
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} else {
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dml_clk_table->dppclk.clk_values_khz[i] = 0;
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dml_clk_table->dppclk.num_clk_values = i;
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}
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} else {
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dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000;
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}
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} else {
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dml_clk_table->dppclk.clk_values_khz[i] = 0;
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}
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}
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}
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/* dtbclk */
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if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) {
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dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
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for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
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if (i < dml_clk_table->dtbclk.num_clk_values) {
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if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz &&
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dc_clk_table->entries[i].dtbclk_mhz > dc_bw_params->dc_mode_limit.dtbclk_mhz) {
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if (i == 0 || dc_clk_table->entries[i-1].dtbclk_mhz < dc_bw_params->dc_mode_limit.dtbclk_mhz) {
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dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000;
|
||||
dml_clk_table->dtbclk.num_clk_values = i + 1;
|
||||
} else {
|
||||
dml_clk_table->dtbclk.clk_values_khz[i] = 0;
|
||||
dml_clk_table->dtbclk.num_clk_values = i;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->dtbclk.clk_values_khz[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* socclk */
|
||||
if (dc_clk_table->num_entries_per_clk.num_socclk_levels) {
|
||||
dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels;
|
||||
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
|
||||
if (i < dml_clk_table->socclk.num_clk_values) {
|
||||
if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.socclk_mhz &&
|
||||
dc_clk_table->entries[i].socclk_mhz > dc_bw_params->dc_mode_limit.socclk_mhz) {
|
||||
if (i == 0 || dc_clk_table->entries[i-1].socclk_mhz < dc_bw_params->dc_mode_limit.socclk_mhz) {
|
||||
dml_clk_table->socclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.socclk_mhz * 1000;
|
||||
dml_clk_table->socclk.num_clk_values = i + 1;
|
||||
} else {
|
||||
dml_clk_table->socclk.clk_values_khz[i] = 0;
|
||||
dml_clk_table->socclk.num_clk_values = i;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->socclk.clk_values_khz[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* do not override phyclks for now */
|
||||
/* phyclk */
|
||||
// dml_clk_table->phyclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_phyclk_levels;
|
||||
// for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {
|
||||
// dml_clk_table->phyclk.clk_values_khz[i] = dc_clk_table->entries[i].phyclk_mhz * 1000;
|
||||
// }
|
||||
|
||||
/* phyclk_d18 */
|
||||
// dml_clk_table->phyclk_d18.num_clk_values = dc_clk_table->num_entries_per_clk.num_phyclk_d18_levels;
|
||||
// for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {
|
||||
// dml_clk_table->phyclk_d18.clk_values_khz[i] = dc_clk_table->entries[i].phyclk_d18_mhz * 1000;
|
||||
// }
|
||||
|
||||
/* phyclk_d32 */
|
||||
// dml_clk_table->phyclk_d32.num_clk_values = dc_clk_table->num_entries_per_clk.num_phyclk_d32_levels;
|
||||
// for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {
|
||||
// dml_clk_table->phyclk_d32.clk_values_khz[i] = dc_clk_table->entries[i].phyclk_d32_mhz * 1000;
|
||||
// }
|
||||
}
|
||||
|
||||
dml_soc_bb->dchub_refclk_mhz = in_dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
|
||||
dml_soc_bb->dprefclk_mhz = in_dc->clk_mgr->dprefclk_khz / 1000;
|
||||
dml_soc_bb->xtalclk_mhz = in_dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000;
|
||||
dml_soc_bb->dispclk_dppclk_vco_speed_mhz = in_dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
|
||||
/* fclk */
|
||||
if (dc_clk_table->num_entries_per_clk.num_fclk_levels) {
|
||||
dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels;
|
||||
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
|
||||
if (i < dml_clk_table->fclk.num_clk_values) {
|
||||
if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz &&
|
||||
dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) {
|
||||
if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) {
|
||||
dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000;
|
||||
dml_clk_table->fclk.num_clk_values = i + 1;
|
||||
} else {
|
||||
dml_clk_table->fclk.clk_values_khz[i] = 0;
|
||||
dml_clk_table->fclk.num_clk_values = i;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->fclk.clk_values_khz[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* uclk */
|
||||
if (dc_clk_table->num_entries_per_clk.num_memclk_levels) {
|
||||
dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels;
|
||||
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
|
||||
if (i < dml_clk_table->uclk.num_clk_values) {
|
||||
if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz &&
|
||||
dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) {
|
||||
if (i == 0 || dc_clk_table->entries[i-1].memclk_mhz < dc_bw_params->dc_mode_limit.memclk_mhz) {
|
||||
dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000;
|
||||
dml_clk_table->uclk.num_clk_values = i + 1;
|
||||
} else {
|
||||
dml_clk_table->uclk.clk_values_khz[i] = 0;
|
||||
dml_clk_table->uclk.num_clk_values = i;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->uclk.clk_values_khz[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* dispclk */
|
||||
if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) {
|
||||
dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels;
|
||||
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
|
||||
if (i < dml_clk_table->dispclk.num_clk_values) {
|
||||
if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz &&
|
||||
dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) {
|
||||
if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) {
|
||||
dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000;
|
||||
dml_clk_table->dispclk.num_clk_values = i + 1;
|
||||
} else {
|
||||
dml_clk_table->dispclk.clk_values_khz[i] = 0;
|
||||
dml_clk_table->dispclk.num_clk_values = i;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->dispclk.clk_values_khz[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* dppclk */
|
||||
if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) {
|
||||
dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels;
|
||||
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
|
||||
if (i < dml_clk_table->dppclk.num_clk_values) {
|
||||
if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz &&
|
||||
dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) {
|
||||
if (i == 0 || dc_clk_table->entries[i-1].dppclk_mhz < dc_bw_params->dc_mode_limit.dppclk_mhz) {
|
||||
dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000;
|
||||
dml_clk_table->dppclk.num_clk_values = i + 1;
|
||||
} else {
|
||||
dml_clk_table->dppclk.clk_values_khz[i] = 0;
|
||||
dml_clk_table->dppclk.num_clk_values = i;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->dppclk.clk_values_khz[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* dtbclk */
|
||||
if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) {
|
||||
dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
|
||||
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
|
||||
if (i < dml_clk_table->dtbclk.num_clk_values) {
|
||||
if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz &&
|
||||
dc_clk_table->entries[i].dtbclk_mhz > dc_bw_params->dc_mode_limit.dtbclk_mhz) {
|
||||
if (i == 0 || dc_clk_table->entries[i-1].dtbclk_mhz < dc_bw_params->dc_mode_limit.dtbclk_mhz) {
|
||||
dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000;
|
||||
dml_clk_table->dtbclk.num_clk_values = i + 1;
|
||||
} else {
|
||||
dml_clk_table->dtbclk.clk_values_khz[i] = 0;
|
||||
dml_clk_table->dtbclk.num_clk_values = i;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->dtbclk.clk_values_khz[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* socclk */
|
||||
if (dc_clk_table->num_entries_per_clk.num_socclk_levels) {
|
||||
dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels;
|
||||
for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
|
||||
if (i < dml_clk_table->socclk.num_clk_values) {
|
||||
if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.socclk_mhz &&
|
||||
dc_clk_table->entries[i].socclk_mhz > dc_bw_params->dc_mode_limit.socclk_mhz) {
|
||||
if (i == 0 || dc_clk_table->entries[i-1].socclk_mhz < dc_bw_params->dc_mode_limit.socclk_mhz) {
|
||||
dml_clk_table->socclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.socclk_mhz * 1000;
|
||||
dml_clk_table->socclk.num_clk_values = i + 1;
|
||||
} else {
|
||||
dml_clk_table->socclk.clk_values_khz[i] = 0;
|
||||
dml_clk_table->socclk.num_clk_values = i;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000;
|
||||
}
|
||||
} else {
|
||||
dml_clk_table->socclk.clk_values_khz[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void override_dml_init_with_values_from_vbios(
|
||||
struct dml2_initialize_instance_in_out *dml_init,
|
||||
const struct dml2_configuration_options *config,
|
||||
const struct dc *in_dc)
|
||||
{
|
||||
const struct clk_bw_params *dc_bw_params = in_dc->clk_mgr->bw_params;
|
||||
struct dml2_soc_bb *dml_soc_bb = &dml_init->soc_bb;
|
||||
struct dml2_soc_state_table *dml_clk_table = &dml_init->soc_bb.clk_table;
|
||||
|
||||
/* override bounding box paramters from VBIOS */
|
||||
if (in_dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns > 0)
|
||||
dml_soc_bb->power_management_parameters.dram_clk_change_blackout_us =
|
||||
(in_dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns + 9) / 10;
|
||||
|
|
@ -317,32 +293,120 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in
|
|||
dml_clk_table->dram_config.channel_width_bytes = in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
|
||||
}
|
||||
|
||||
/* override bounding box paramters from DC config */
|
||||
if (in_dc->bb_overrides.sr_exit_time_ns) {
|
||||
dml_soc_bb->power_management_parameters.stutter_exit_latency_us =
|
||||
dml_init->soc_bb.xtalclk_mhz = in_dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000;
|
||||
}
|
||||
|
||||
|
||||
static void override_dml_init_with_values_from_dmub(struct dml2_initialize_instance_in_out *dml_init,
|
||||
const struct dml2_configuration_options *config,
|
||||
const struct dc *in_dc)
|
||||
{
|
||||
/*
|
||||
* TODO - There seems to be overlaps between the values overriden from
|
||||
* dmub and vbios. Investigate and identify the values that DMUB needs
|
||||
* to own.
|
||||
*/
|
||||
// const struct dmub_soc_bb_params *dmub_bb_params =
|
||||
// (const struct dmub_soc_bb_params *)config->bb_from_dmub;
|
||||
|
||||
// if (dmub_bb_params == NULL)
|
||||
// return;
|
||||
|
||||
// if (dmub_bb_params->dram_clk_change_blackout_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.dram_clk_change_blackout_us =
|
||||
// (double) dmub_bb_params->dram_clk_change_blackout_ns / 1000.0;
|
||||
// if (dmub_bb_params->dram_clk_change_read_only_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.dram_clk_change_read_only_us =
|
||||
// (double) dmub_bb_params->dram_clk_change_read_only_ns / 1000.0;
|
||||
// if (dmub_bb_params->dram_clk_change_write_only_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.dram_clk_change_write_only_us =
|
||||
// (double) dmub_bb_params->dram_clk_change_write_only_ns / 1000.0;
|
||||
// if (dmub_bb_params->fclk_change_blackout_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.fclk_change_blackout_us =
|
||||
// (double) dmub_bb_params->fclk_change_blackout_ns / 1000.0;
|
||||
// if (dmub_bb_params->g7_ppt_blackout_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.g7_ppt_blackout_us =
|
||||
// (double) dmub_bb_params->g7_ppt_blackout_ns / 1000.0;
|
||||
// if (dmub_bb_params->stutter_enter_plus_exit_latency_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.stutter_enter_plus_exit_latency_us =
|
||||
// (double) dmub_bb_params->stutter_enter_plus_exit_latency_ns / 1000.0;
|
||||
// if (dmub_bb_params->stutter_exit_latency_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.stutter_exit_latency_us =
|
||||
// (double) dmub_bb_params->stutter_exit_latency_ns / 1000.0;
|
||||
// if (dmub_bb_params->z8_stutter_enter_plus_exit_latency_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.z8_stutter_enter_plus_exit_latency_us =
|
||||
// (double) dmub_bb_params->z8_stutter_enter_plus_exit_latency_ns / 1000.0;
|
||||
// if (dmub_bb_params->z8_stutter_exit_latency_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.z8_stutter_exit_latency_us =
|
||||
// (double) dmub_bb_params->z8_stutter_exit_latency_ns / 1000.0;
|
||||
// if (dmub_bb_params->z8_min_idle_time_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.z8_min_idle_time =
|
||||
// (double) dmub_bb_params->z8_min_idle_time_ns / 1000.0;
|
||||
// #ifndef TRIM_DML2_DCN6B_IP_SENSITIVE
|
||||
// if (dmub_bb_params->type_b_dram_clk_change_blackout_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.lpddr5_dram_clk_change_blackout_us =
|
||||
// (double) dmub_bb_params->type_b_dram_clk_change_blackout_ns / 1000.0;
|
||||
// if (dmub_bb_params->type_b_ppt_blackout_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.lpddr5_ppt_blackout_us =
|
||||
// (double) dmub_bb_params->type_b_ppt_blackout_ns / 1000.0;
|
||||
// #else
|
||||
// if (dmub_bb_params->type_b_dram_clk_change_blackout_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.type_b_dram_clk_change_blackout_us =
|
||||
// (double) dmub_bb_params->type_b_dram_clk_change_blackout_ns / 1000.0;
|
||||
// if (dmub_bb_params->type_b_ppt_blackout_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.type_b_ppt_blackout_us =
|
||||
// (double) dmub_bb_params->type_b_ppt_blackout_ns / 1000.0;
|
||||
// #endif
|
||||
// if (dmub_bb_params->vmin_limit_dispclk_khz > 0)
|
||||
// dml_init->soc_bb.vmin_limit.dispclk_khz = dmub_bb_params->vmin_limit_dispclk_khz;
|
||||
// if (dmub_bb_params->vmin_limit_dcfclk_khz > 0)
|
||||
// dml_init->soc_bb.vmin_limit.dcfclk_khz = dmub_bb_params->vmin_limit_dcfclk_khz;
|
||||
// if (dmub_bb_params->g7_temperature_read_blackout_ns > 0)
|
||||
// dml_init->soc_bb.power_management_parameters.g7_temperature_read_blackout_us =
|
||||
// (double) dmub_bb_params->g7_temperature_read_blackout_ns / 1000.0;
|
||||
}
|
||||
|
||||
static void override_dml_init_with_values_from_software_policy(struct dml2_initialize_instance_in_out *dml_init,
|
||||
const struct dml2_configuration_options *config,
|
||||
const struct dc *in_dc)
|
||||
{
|
||||
if (!config->use_native_soc_bb_construction) {
|
||||
dml_init->soc_bb = config->external_socbb_ip_params->soc_bb;
|
||||
dml_init->ip_caps = config->external_socbb_ip_params->ip_params;
|
||||
}
|
||||
|
||||
if (in_dc->bb_overrides.sr_exit_time_ns)
|
||||
dml_init->soc_bb.power_management_parameters.stutter_exit_latency_us =
|
||||
in_dc->bb_overrides.sr_exit_time_ns / 1000.0;
|
||||
}
|
||||
|
||||
if (in_dc->bb_overrides.sr_enter_plus_exit_time_ns) {
|
||||
dml_soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us =
|
||||
if (in_dc->bb_overrides.sr_enter_plus_exit_time_ns)
|
||||
dml_init->soc_bb.power_management_parameters.stutter_enter_plus_exit_latency_us =
|
||||
in_dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
|
||||
}
|
||||
|
||||
if (in_dc->bb_overrides.dram_clock_change_latency_ns) {
|
||||
dml_soc_bb->power_management_parameters.dram_clk_change_blackout_us =
|
||||
if (in_dc->bb_overrides.dram_clock_change_latency_ns)
|
||||
dml_init->soc_bb.power_management_parameters.dram_clk_change_blackout_us =
|
||||
in_dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
|
||||
}
|
||||
|
||||
if (in_dc->bb_overrides.fclk_clock_change_latency_ns) {
|
||||
dml_soc_bb->power_management_parameters.fclk_change_blackout_us =
|
||||
if (in_dc->bb_overrides.fclk_clock_change_latency_ns)
|
||||
dml_init->soc_bb.power_management_parameters.fclk_change_blackout_us =
|
||||
in_dc->bb_overrides.fclk_clock_change_latency_ns / 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
//TODO
|
||||
// if (in_dc->bb_overrides.dummy_clock_change_latency_ns) {
|
||||
// dml_soc_bb->power_management_parameters.dram_clk_change_blackout_us =
|
||||
// in_dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
|
||||
// }
|
||||
void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init,
|
||||
const struct dml2_configuration_options *config,
|
||||
const struct dc *in_dc)
|
||||
{
|
||||
populate_default_dml_init_params(dml_init, config, in_dc);
|
||||
|
||||
override_dml_init_with_values_from_hardware_default(dml_init, config, in_dc);
|
||||
|
||||
override_dml_init_with_values_from_smu(dml_init, config, in_dc);
|
||||
|
||||
override_dml_init_with_values_from_vbios(dml_init, config, in_dc);
|
||||
|
||||
override_dml_init_with_values_from_dmub(dml_init, config, in_dc);
|
||||
|
||||
override_dml_init_with_values_from_software_policy(dml_init, config, in_dc);
|
||||
}
|
||||
|
||||
static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
|
||||
|
|
|
|||
|
|
@ -17,9 +17,7 @@ struct dml2_context;
|
|||
struct dml2_configuration_options;
|
||||
struct dml2_initialize_instance_in_out;
|
||||
|
||||
void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);
|
||||
void dml21_initialize_soc_bb_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);
|
||||
void dml21_initialize_ip_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);
|
||||
void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc);
|
||||
bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml_ctx);
|
||||
void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state *context);
|
||||
void dml21_extract_watermark_sets(const struct dc *in_dc, union dcn_watermark_set *watermarks, struct dml2_context *in_ctx);
|
||||
|
|
|
|||
|
|
@ -35,15 +35,11 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx)
|
|||
return true;
|
||||
}
|
||||
|
||||
static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)
|
||||
static void dml21_populate_configuration_options(const struct dc *in_dc,
|
||||
struct dml2_context *dml_ctx,
|
||||
const struct dml2_configuration_options *config)
|
||||
{
|
||||
bool disable_fams2;
|
||||
struct dml2_pmo_options *pmo_options = &dml_ctx->v21.dml_init.options.pmo_options;
|
||||
|
||||
/* ODM options */
|
||||
pmo_options->disable_dyn_odm = !config->minimize_dispclk_using_odm;
|
||||
pmo_options->disable_dyn_odm_for_multi_stream = true;
|
||||
pmo_options->disable_dyn_odm_for_stream_with_svp = true;
|
||||
dml_ctx->config = *config;
|
||||
|
||||
/* UCLK P-State options */
|
||||
if (in_dc->debug.dml21_force_pstate_method) {
|
||||
|
|
@ -53,52 +49,20 @@ static void dml21_apply_debug_options(const struct dc *in_dc, struct dml2_contex
|
|||
} else {
|
||||
dml_ctx->config.pmo.force_pstate_method_enable = false;
|
||||
}
|
||||
|
||||
pmo_options->disable_vblank = ((in_dc->debug.dml21_disable_pstate_method_mask >> 1) & 1);
|
||||
|
||||
/* NOTE: DRR and SubVP Require FAMS2 */
|
||||
disable_fams2 = !in_dc->debug.fams2_config.bits.enable;
|
||||
pmo_options->disable_svp = ((in_dc->debug.dml21_disable_pstate_method_mask >> 2) & 1) ||
|
||||
in_dc->debug.force_disable_subvp ||
|
||||
disable_fams2;
|
||||
pmo_options->disable_drr_clamped = ((in_dc->debug.dml21_disable_pstate_method_mask >> 3) & 1) ||
|
||||
disable_fams2;
|
||||
pmo_options->disable_drr_var = ((in_dc->debug.dml21_disable_pstate_method_mask >> 4) & 1) ||
|
||||
disable_fams2;
|
||||
pmo_options->disable_fams2 = disable_fams2;
|
||||
|
||||
pmo_options->disable_drr_var_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE ||
|
||||
in_dc->debug.disable_fams_gaming == INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY;
|
||||
pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE;
|
||||
}
|
||||
|
||||
static void dml21_init(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)
|
||||
static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)
|
||||
{
|
||||
switch (in_dc->ctx->dce_version) {
|
||||
case DCN_VERSION_4_01:
|
||||
(*dml_ctx)->v21.dml_init.options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp;
|
||||
break;
|
||||
default:
|
||||
(*dml_ctx)->v21.dml_init.options.project_id = dml2_project_invalid;
|
||||
}
|
||||
|
||||
(*dml_ctx)->architecture = dml2_architecture_21;
|
||||
dml_ctx->architecture = dml2_architecture_21;
|
||||
|
||||
/* Store configuration options */
|
||||
(*dml_ctx)->config = *config;
|
||||
dml21_populate_configuration_options(in_dc, dml_ctx, config);
|
||||
|
||||
DC_FP_START();
|
||||
|
||||
/*Initialize SOCBB and DCNIP params */
|
||||
dml21_initialize_soc_bb_params(&(*dml_ctx)->v21.dml_init, config, in_dc);
|
||||
dml21_initialize_ip_params(&(*dml_ctx)->v21.dml_init, config, in_dc);
|
||||
dml21_apply_soc_bb_overrides(&(*dml_ctx)->v21.dml_init, config, in_dc);
|
||||
dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, config, in_dc);
|
||||
|
||||
/* apply debug overrides */
|
||||
dml21_apply_debug_options(in_dc, *dml_ctx, config);
|
||||
|
||||
/*Initialize DML21 instance */
|
||||
dml2_initialize_instance(&(*dml_ctx)->v21.dml_init);
|
||||
dml2_initialize_instance(&dml_ctx->v21.dml_init);
|
||||
|
||||
DC_FP_END();
|
||||
}
|
||||
|
|
@ -109,7 +73,7 @@ bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const s
|
|||
if (!dml21_allocate_memory(dml_ctx))
|
||||
return false;
|
||||
|
||||
dml21_init(in_dc, dml_ctx, config);
|
||||
dml21_init(in_dc, *dml_ctx, config);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -495,7 +459,7 @@ bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
|
|||
return true;
|
||||
}
|
||||
|
||||
void dml21_reinit(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)
|
||||
void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config)
|
||||
{
|
||||
dml21_init(in_dc, dml_ctx, config);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ void dml21_copy(struct dml2_context *dst_dml_ctx,
|
|||
struct dml2_context *src_dml_ctx);
|
||||
bool dml21_create_copy(struct dml2_context **dst_dml_ctx,
|
||||
struct dml2_context *src_dml_ctx);
|
||||
void dml21_reinit(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config);
|
||||
void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const struct dml2_configuration_options *config);
|
||||
|
||||
/**
|
||||
* dml21_validate - Determines if a display configuration is supported or not.
|
||||
|
|
|
|||
|
|
@ -580,8 +580,8 @@ static inline struct dml2_context *dml2_allocate_memory(void)
|
|||
|
||||
static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
|
||||
{
|
||||
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version == DCN_VERSION_4_01)) {
|
||||
dml21_reinit(in_dc, dml2, config);
|
||||
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) {
|
||||
dml21_reinit(in_dc, *dml2, config);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -626,9 +626,7 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op
|
|||
bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
|
||||
{
|
||||
// TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete.
|
||||
if ((in_dc->debug.using_dml21)
|
||||
&& (in_dc->ctx->dce_version == DCN_VERSION_4_01
|
||||
))
|
||||
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01))
|
||||
return dml21_create(in_dc, dml2, config);
|
||||
|
||||
// Allocate Mode Lib Ctx
|
||||
|
|
@ -697,8 +695,8 @@ void dml2_reinit(const struct dc *in_dc,
|
|||
const struct dml2_configuration_options *config,
|
||||
struct dml2_context **dml2)
|
||||
{
|
||||
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version == DCN_VERSION_4_01)) {
|
||||
dml21_reinit(in_dc, dml2, config);
|
||||
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) {
|
||||
dml21_reinit(in_dc, *dml2, config);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user