From 86ebfbf1fb152f1898fdc9a70005f7ffad083b48 Mon Sep 17 00:00:00 2001 From: Jakub Kolakowski Date: Tue, 31 Mar 2026 15:22:59 +0000 Subject: [PATCH] drm/xe/sriov: Mark NVL as SR-IOV capable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable SR-IOV support for NVL platforms. Signed-off-by: Jakub Kolakowski Cc: Michal Wajdeczko Cc: Piotr Piórkowski Cc: Dnyaneshwar Bhadane Cc: Matt Roper Reviewed-by: Tomasz Lis Link: https://patch.msgid.link/20260331152259.58270-1-jakub1.kolakowski@intel.com Signed-off-by: Matt Roper --- drivers/gpu/drm/xe/xe_pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 12d3be7f9f6c..1243c7d8ed10 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -444,6 +444,7 @@ static const struct xe_device_desc nvls_desc = { .has_display = true, .has_flat_ccs = 1, .has_pre_prod_wa = 1, + .has_sriov = true, .max_gt_per_tile = 2, MULTI_LRC_MASK, .require_force_probe = true, @@ -482,6 +483,7 @@ static const struct xe_device_desc nvlp_desc = { .has_flat_ccs = 1, .has_page_reclaim_hw_assist = true, .has_pre_prod_wa = true, + .has_sriov = true, .max_gt_per_tile = 2, MULTI_LRC_MASK, .require_force_probe = true,