github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-31 10:33:41 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

cxl/port: Move decoder setup before dport creation

Browse Source 
There are port setup actions that run on first dport arrival, and there are
setup actions that run per dport.

RAS register setup is a future additional setup action to run per-port
(once the first dport arrives), and each dport also has RAS registers to
map.

Before adding that, flip the order of "first dport" and "per-dport"
actions. This makes allocation symmetric with teardown, "first dport"
actions unwind after last dport removed. It also allows for using a devres
group to collect the unrelated decoder, RAS, and dport setup actions into
one group release action.

The new cxl_port_open_group() collects "first dport" and "per-dport" into
one group that can be released on any failure. This group's lifetime only
needs to span the short duration of cxl_port_add_dport() to cleanup all
potential damage from failing to add a dport. Contrast that to the "dport"
devres group that is called upon to destruct fully formed dport objects.

Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Tested-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20260131000403.2135324-5-dan.j.williams@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
This commit is contained in:
Dan Williams 2026-01-30 16:03:58 -08:00 committed by Dave Jiang
parent afa2bdba1e
commit 86e756715d
1 changed files with 21 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
drivers/cxl/core/port.c
View File

@ -1651,10 +1651,14 @@ static bool dport_exists(struct cxl_port *port, struct device *dport_dev)
return false;
}
DEFINE_FREE(del_cxl_dport, struct cxl_dport *, if (!IS_ERR_OR_NULL(_T)) del_dport(_T))
/* note this implicitly casts the group back to its @port */
DEFINE_FREE(cxl_port_release_dr_group, struct cxl_port *,
if (_T) devres_release_group(&_T->dev, _T))
static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
struct device *dport_dev)
{
struct cxl_dport *dport;
int rc;
device_lock_assert(&port->dev);
@ -1664,14 +1668,13 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
if (dport_exists(port, dport_dev))
return ERR_PTR(-EBUSY);
struct cxl_dport *dport __free(del_cxl_dport) =
devm_cxl_add_dport_by_dev(port, dport_dev);
if (IS_ERR(dport))
return dport;
/* Temp group for all "first dport" and "per dport" setup actions */
void *port_dr_group __free(cxl_port_release_dr_group) =
devres_open_group(&port->dev, port, GFP_KERNEL);
if (!port_dr_group)
return ERR_PTR(-ENOMEM);
cxl_switch_parse_cdat(dport);
if (port->nr_dports == 1) {
if (port->nr_dports == 0) {
/*
* Some host bridges are known to not have component regsisters
* available until a root port has trained CXL. Perform that
@ -1684,18 +1687,24 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port,
rc = devm_cxl_switch_port_decoders_setup(port);
if (rc)
return ERR_PTR(rc);
dev_dbg(&port->dev, "first dport%d:%s added with decoders\n",
dport->port_id, dev_name(dport_dev));
return no_free_ptr(dport);
}
dport = devm_cxl_add_dport_by_dev(port, dport_dev);
if (IS_ERR(dport))
return dport;
/* This group was only needed for early exit above */
devres_remove_group(&port->dev, no_free_ptr(port_dr_group));
cxl_switch_parse_cdat(dport);
/* New dport added, update the decoder targets */
device_for_each_child(&port->dev, dport, update_decoder_targets);
dev_dbg(&port->dev, "dport%d:%s added\n", dport->port_id,
dev_name(dport_dev));
return no_free_ptr(dport);
return dport;
}
static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev,