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arm64: dts: rockchip: support Ethernet Switch adapter for RK3588 Jaguar
This adds support for the Ethernet Switch adapter connected to the mezzanine connector on RK3588 Jaguar. This adapter has a KSZ9896 Ethernet Switch with 4 1GbE Ethernet connectors, two user controllable LEDs, and an M12 12-pin connector which exposes the following signals: - RS232/RS485 (max 250Kbps/500Kbps, RX pin1, TX pin2) - two digital inputs (pin4 routed to GPIO3_C5 on SoC, pin5 to GPIO4_B4) - two digital outputs (pin7 routed to GPIO3_D3 on SoC, pin8 to GPIO3_D1) - two analog inputs (pin10 to channel1 of ADS1015, pin11 to channel2) Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> [Andrew's review for gmac1 and switch@5f parts] Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20250604-jaguar-mezz-eth-switch-v3-1-c68123240f9e@cherry.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Quentin Schulz
Heiko Stuebner
parent
6b28769116
commit
8674f05975
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@ -160,6 +160,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-firefly-itx-3588j.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-friendlyelec-cm3588-nas.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h96-max-v58.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-ethernet-switch.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mnt-reform2.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
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@ -233,6 +234,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-wifi.dtb
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rk3588-edgeble-neu6b-wifi-dtbs := rk3588-edgeble-neu6b-io.dtb \
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rk3588-edgeble-neu6a-wifi.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-ethernet-switch.dtb
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rk3588-jaguar-ethernet-switch-dtbs := rk3588-jaguar.dtb \
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rk3588-jaguar-ethernet-switch.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar-pre-ict-tester.dtb
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rk3588-jaguar-pre-ict-tester-dtbs := rk3588-jaguar.dtb \
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rk3588-jaguar-pre-ict-tester.dtbo
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195
arch/arm64/boot/dts/rockchip/rk3588-jaguar-ethernet-switch.dtso
Normal file
195
arch/arm64/boot/dts/rockchip/rk3588-jaguar-ethernet-switch.dtso
Normal file
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@ -0,0 +1,195 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2025 Cherry Embedded Solutions GmbH
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*
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* Device Tree Overlay for the Ethernet Switch adapter for the Mezzanine
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* connector on RK3588 Jaguar
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* (manual: https://embedded.cherry.de/jaguar-ethernet-switch-user-manual/)
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*
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* This adapter has a KSZ9896 Ethernet Switch with 4 1GbE Ethernet connectors,
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* two user controllable LEDs, and an M12 12-pin connector which exposes the
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* following signals:
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* - RS232/RS485 (max 250Kbps/500Kbps, RX pin1, TX pin2)
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* - two digital inputs (pin4 routed to GPIO3_C5 on SoC, pin5 to GPIO4_B4)
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* - two digital outputs (pin7 routed to GPIO3_D3 on SoC, pin8 to GPIO3_D1)
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* - two analog inputs (pin10 to channel1 of ADS1015, pin11 to channel2)
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*
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* RK3588 Jaguar can be powered entirely through the adapter via the M8 3-pin
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* connector (12-24V).
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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&{/} {
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aliases {
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ethernet1 = "/ethernet@fe1c0000";
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};
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mezzanine-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&led_usr1_pin &led_usr2_pin>;
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led-1 {
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gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
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label = "USR1";
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};
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led-2 {
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gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
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label = "USR2";
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};
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};
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};
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&gmac1 {
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clock_in_out = "output";
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1_rx_bus2
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&gmac1_tx_bus2
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&gmac1_rgmii_clk
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&gmac1_rgmii_bus
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ð1_pins>;
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rx_delay = <0x0>;
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tx_delay = <0x0>;
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&i2c1 {
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#address-cells = <1>;
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/*
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* ADS1015 can handle high-speed (HS) mode (up to 3.4MHz) on I2C bus,
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* but SoC can handle only up to 400kHz.
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*/
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clock-frequency = <400000>;
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#size-cells = <0>;
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status = "okay";
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adc@48 {
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compatible = "ti,ads1015";
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reg = <0x48>;
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#address-cells = <1>;
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interrupt-parent = <&gpio3>;
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interrupts = <RK_PC7 IRQ_TYPE_EDGE_FALLING>;
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pinctrl-0 = <&adc_alert>;
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pinctrl-names = "default";
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#io-channel-cells = <1>;
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#size-cells = <0>;
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channel@1 {
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reg = <5>; /* Single-ended between AIN1 and GND */
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ti,datarate = <0>;
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ti,gain = <5>;
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};
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channel@2 {
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reg = <6>; /* Single-ended between AIN2 and GND */
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ti,datarate = <0>;
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ti,gain = <5>;
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};
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};
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switch@5f {
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compatible = "microchip,ksz9896";
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reg = <0x5f>;
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interrupt-parent = <&gpio3>;
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interrupts = <RK_PB7 IRQ_TYPE_EDGE_FALLING>; /* ETH_INTRP_N */
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pinctrl-0 = <ð_reset_n ð_intrp_n>;
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pinctrl-names = "default";
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reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; /* ETH_RESET */
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microchip,synclko-disable; /* CLKO_25_125 only routed to TP1 */
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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lan1: port@0 {
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reg = <0>;
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label = "ETH1";
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};
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lan2: port@1 {
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reg = <1>;
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label = "ETH2";
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};
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lan3: port@2 {
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reg = <2>;
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label = "ETH3";
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};
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lan4: port@3 {
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reg = <3>;
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label = "ETH4";
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};
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port@5 {
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reg = <5>;
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ethernet = <&gmac1>;
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label = "CPU";
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <2000>;
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tx-internal-delay-ps = <2000>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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&pinctrl {
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adc {
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adc_alert: adc-alert-irq {
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rockchip,pins =
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<3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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ethernet {
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eth_intrp_n: eth-intrp-n {
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rockchip,pins =
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<3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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eth_reset_n: eth-reset-n {
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rockchip,pins =
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<3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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leds {
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led_usr1_pin: led-usr1-pin {
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rockchip,pins =
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<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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led_usr2_pin: led-usr2-pin {
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rockchip,pins =
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<3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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&uart9 {
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/* GPIO3_D0/EN_RS485_MODE for switching between RS232 and RS485 */
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pinctrl-0 = <&uart9m2_xfer &uart9m2_rtsn>;
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pinctrl-names = "default";
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linux,rs485-enabled-at-boot-time;
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status = "okay";
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};
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