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arm64: dts: imx8mp: Add pclk clock and second power domain for the ISP

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The ISP HDR stitching registers are clocked by the pixel clock, which is
gated by the MIPI_CSI2 power domain. Attempting to access those
registers with the clock off locks up the system. Fix this by adding the
pclk clock and the MIPI_CSI2 secondary power domain.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Laurent Pinchart 2025-06-16 04:11:15 +03:00 committed by Shawn Guo
parent 5a796a700f
commit 8647d8a770
1 changed files with 12 additions and 6 deletions
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18
arch/arm64/boot/dts/freescale/imx8mp.dtsi
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@ -1701,9 +1701,12 @@ isp_0: isp@32e10000 {
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "isp", "aclk", "hclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>;
clock-names = "isp", "aclk", "hclk", "pclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>,
<&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
power-domain-names = "isp", "csi2";
fsl,blk-ctrl = <&media_blk_ctrl 0>;
status = "disabled";
@ -1723,9 +1726,12 @@ isp_1: isp@32e20000 {
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "isp", "aclk", "hclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>;
clock-names = "isp", "aclk", "hclk", "pclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>,
<&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
power-domain-names = "isp", "csi2";
fsl,blk-ctrl = <&media_blk_ctrl 1>;
status = "disabled";