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Merge branch 'dt-bindings-net-convert-fsl-fman-related-file-to-yaml-format'
Frank Li says: ==================== dt-bindings: net: Convert fsl,fman related file to yaml format Passed dt_binding_check Run dt_binding_check: fsl,fman-mdio.yaml SCHEMA Documentation/devicetree/bindings/processed-schema.json CHKDT Documentation/devicetree/bindings LINT Documentation/devicetree/bindings DTEX Documentation/devicetree/bindings/net/fsl,fman-mdio.example.dts DTC_CHK Documentation/devicetree/bindings/net/fsl,fman-mdio.example.dtb Run dt_binding_check: fsl,fman-muram.yaml SCHEMA Documentation/devicetree/bindings/processed-schema.json CHKDT Documentation/devicetree/bindings LINT Documentation/devicetree/bindings DTEX Documentation/devicetree/bindings/net/fsl,fman-muram.example.dts DTC_CHK Documentation/devicetree/bindings/net/fsl,fman-muram.example.dtb Run dt_binding_check: fsl,fman-port.yaml SCHEMA Documentation/devicetree/bindings/processed-schema.json CHKDT Documentation/devicetree/bindings LINT Documentation/devicetree/bindings DTEX Documentation/devicetree/bindings/net/fsl,fman-port.example.dts DTC_CHK Documentation/devicetree/bindings/net/fsl,fman-port.example.dtb Run dt_binding_check: fsl,fman.yaml SCHEMA Documentation/devicetree/bindings/processed-schema.json CHKDT Documentation/devicetree/bindings LINT Documentation/devicetree/bindings DTEX Documentation/devicetree/bindings/net/fsl,fman.example.dts DTC_CHK Documentation/devicetree/bindings/net/fsl,fman.example.dtb Run dt_binding_check: ptp-qoriq.yaml SCHEMA Documentation/devicetree/bindings/processed-schema.json CHKDT Documentation/devicetree/bindings LINT Documentation/devicetree/bindings DTEX Documentation/devicetree/bindings/ptp/ptp-qoriq.example.dts DTC_CHK Documentation/devicetree/bindings/ptp/ptp-qoriq.example.dtb v1: https://lore.kernel.org/r/20240614-ls_fman-v1-0-cb33c96dc799@nxp.com ==================== Link: https://patch.msgid.link/20240618-ls_fman-v2-0-f00a82623d8e@nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
86474deeb5
123
Documentation/devicetree/bindings/net/fsl,fman-mdio.yaml
Normal file
123
Documentation/devicetree/bindings/net/fsl,fman-mdio.yaml
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|
|
@ -0,0 +1,123 @@
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|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Frame Manager MDIO Device
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
description: FMan MDIO Node.
|
||||
The MDIO is a bus to which the PHY devices are connected.
|
||||
|
||||
properties:
|
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compatible:
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enum:
|
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- fsl,fman-mdio
|
||||
- fsl,fman-xmdio
|
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- fsl,fman-memac-mdio
|
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description:
|
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Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
|
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Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
|
||||
Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
|
||||
FMan v3.
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: A reference to the input clock of the controller
|
||||
from which the MDC frequency is derived.
|
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|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
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fsl,fman-internal-mdio:
|
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$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Fman has internal MDIO for internal PCS(Physical
|
||||
Coding Sublayer) PHYs and external MDIO for external PHYs.
|
||||
The settings and programming routines for internal/external
|
||||
MDIO are different. Must be included for internal MDIO.
|
||||
|
||||
fsl,erratum-a009885:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Indicates the presence of the A009885
|
||||
erratum describing that the contents of MDIO_DATA may
|
||||
become corrupt unless it is read within 16 MDC cycles
|
||||
of MDIO_CFG[BSY] being cleared, when performing an
|
||||
MDIO read operation.
|
||||
|
||||
fsl,erratum-a011043:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
Indicates the presence of the A011043 erratum
|
||||
describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
|
||||
set when reading internal PCS registers. MDIO reads to
|
||||
internal PCS registers may result in having the
|
||||
MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
|
||||
read data (MDIO_DATA[MDIO_DATA]) is correct.
|
||||
Software may get false read error when reading internal
|
||||
PCS registers through MDIO. As a workaround, all internal
|
||||
MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
|
||||
|
||||
For internal PHY device on internal mdio bus, a PHY node should be created.
|
||||
See the definition of the PHY node in booting-without-of.txt for an
|
||||
example of how to define a PHY (Internal PHY has no interrupt line).
|
||||
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
|
||||
- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
|
||||
The PCS PHY address should correspond to the value of the appropriate
|
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MDEV_PORT.
|
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|
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little-endian:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
IP block is little-endian mode. The default endian mode is big-endian.
|
||||
|
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required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- $ref: mdio.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mdio@f1000 {
|
||||
compatible = "fsl,fman-xmdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
interrupts = <101 2 0 0>;
|
||||
};
|
||||
|
||||
- |
|
||||
mdio@e3120 {
|
||||
compatible = "fsl,fman-mdio";
|
||||
reg = <0xe3120 0xee0>;
|
||||
fsl,fman-internal-mdio;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tbi-phy@8 {
|
||||
reg = <0x8>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
mdio@f1000 {
|
||||
compatible = "fsl,fman-memac-mdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
fsl,fman-internal-mdio;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcsphy6: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
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40
Documentation/devicetree/bindings/net/fsl,fman-muram.yaml
Normal file
40
Documentation/devicetree/bindings/net/fsl,fman-muram.yaml
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|
@ -0,0 +1,40 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/fsl,fman-muram.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Frame Manager MURAM Device
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
description: |
|
||||
FMan Internal memory - shared between all the FMan modules.
|
||||
It contains data structures that are common and written to or read by
|
||||
the modules.
|
||||
|
||||
FMan internal memory is split into the following parts:
|
||||
Packet buffering (Tx/Rx FIFOs)
|
||||
Frames internal context
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,fman-muram
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
muram@0 {
|
||||
compatible = "fsl,fman-muram";
|
||||
reg = <0x0 0x28000>;
|
||||
};
|
||||
75
Documentation/devicetree/bindings/net/fsl,fman-port.yaml
Normal file
75
Documentation/devicetree/bindings/net/fsl,fman-port.yaml
Normal file
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|
@ -0,0 +1,75 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/fsl,fman-port.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Frame Manager Port Device
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
description: |
|
||||
The Frame Manager (FMan) supports several types of hardware ports:
|
||||
Ethernet receiver (RX)
|
||||
Ethernet transmitter (TX)
|
||||
Offline/Host command (O/H)
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,fman-v2-port-oh
|
||||
- fsl,fman-v2-port-rx
|
||||
- fsl,fman-v2-port-tx
|
||||
- fsl,fman-v3-port-oh
|
||||
- fsl,fman-v3-port-rx
|
||||
- fsl,fman-v3-port-tx
|
||||
|
||||
cell-index:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Specifies the hardware port id.
|
||||
Each hardware port on the FMan has its own hardware PortID.
|
||||
Super set of all hardware Port IDs available at FMan Reference
|
||||
Manual under "FMan Hardware Ports in Freescale Devices" table.
|
||||
|
||||
Each hardware port is assigned a 4KB, port-specific page in
|
||||
the FMan hardware port memory region (which is part of the
|
||||
FMan memory map). The first 4 KB in the FMan hardware ports
|
||||
memory region is used for what are called common registers.
|
||||
The subsequent 63 4KB pages are allocated to the hardware
|
||||
ports.
|
||||
The page of a specific port is determined by the cell-index.
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: There is one reg region describing the port
|
||||
configuration registers.
|
||||
|
||||
fsl,fman-10g-port:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: The default port rate is 1G.
|
||||
If this property exists, the port is s 10G port.
|
||||
|
||||
fsl,fman-best-effort-port:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: The default port rate is 1G.
|
||||
Can be defined only if 10G-support is set.
|
||||
This property marks a best-effort 10G port (10G port that
|
||||
may not be capable of line rate).
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- cell-index
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
port@a8000 {
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xa8000 0x1000>;
|
||||
cell-index = <0x28>;
|
||||
};
|
||||
|
||||
204
Documentation/devicetree/bindings/net/fsl,fman.yaml
Normal file
204
Documentation/devicetree/bindings/net/fsl,fman.yaml
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/fsl,fman.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Frame Manager Device
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
description:
|
||||
Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
|
||||
etc.) the FMan node will have child nodes for each of them.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,fman
|
||||
description:
|
||||
FMan version can be determined via FM_IP_REV_1 register in the
|
||||
FMan block. The offset is 0xc4 from the beginning of the
|
||||
Frame Processing Manager memory map (0xc3000 from the
|
||||
beginning of the FMan node).
|
||||
|
||||
cell-index:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Specifies the index of the FMan unit.
|
||||
|
||||
The cell-index value may be used by the SoC, to identify the
|
||||
FMan unit in the SoC memory map. In the table below,
|
||||
there's a description of the cell-index use in each SoC:
|
||||
|
||||
- P1023:
|
||||
register[bit] FMan unit cell-index
|
||||
============================================================
|
||||
DEVDISR[1] 1 0
|
||||
|
||||
- P2041, P3041, P4080 P5020, P5040:
|
||||
register[bit] FMan unit cell-index
|
||||
============================================================
|
||||
DCFG_DEVDISR2[6] 1 0
|
||||
DCFG_DEVDISR2[14] 2 1
|
||||
(Second FM available only in P4080 and P5040)
|
||||
|
||||
- B4860, T1040, T2080, T4240:
|
||||
register[bit] FMan unit cell-index
|
||||
============================================================
|
||||
DCFG_CCSR_DEVDISR2[24] 1 0
|
||||
DCFG_CCSR_DEVDISR2[25] 2 1
|
||||
(Second FM available only in T4240)
|
||||
|
||||
DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
|
||||
the specific SoC "Device Configuration/Pin Control" Memory
|
||||
Map.
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: BMI configuration registers.
|
||||
- description: QMI configuration registers.
|
||||
- description: DMA configuration registers.
|
||||
- description: FPM configuration registers.
|
||||
- description: FMan controller configuration registers.
|
||||
minItems: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fmanclk
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: The first element is associated with the event interrupts.
|
||||
- description: the second element is associated with the error interrupts.
|
||||
|
||||
fsl,qman-channel-range:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
Specifies the range of the available dedicated
|
||||
channels in the FMan. The first cell specifies the beginning
|
||||
of the range and the second cell specifies the number of
|
||||
channels
|
||||
items:
|
||||
- description: The first cell specifies the beginning of the range.
|
||||
- description: |
|
||||
The second cell specifies the number of channels.
|
||||
Further information available at:
|
||||
"Work Queue (WQ) Channel Assignments in the QMan" section
|
||||
in DPAA Reference Manual.
|
||||
|
||||
fsl,qman:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: See soc/fsl/qman.txt
|
||||
|
||||
fsl,bman:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: See soc/fsl/bman.txt
|
||||
|
||||
fsl,erratum-a050385:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: A boolean property. Indicates the presence of the
|
||||
erratum A050385 which indicates that DMA transactions that are
|
||||
split can result in a FMan lock.
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
'^muram@[a-f0-9]+$':
|
||||
$ref: fsl,fman-muram.yaml
|
||||
|
||||
'^port@[a-f0-9]+$':
|
||||
$ref: fsl,fman-port.yaml
|
||||
|
||||
'^ethernet@[a-f0-9]+$':
|
||||
$ref: fsl,fman-dtsec.yaml
|
||||
|
||||
'^mdio@[a-f0-9]+$':
|
||||
$ref: fsl,fman-mdio.yaml
|
||||
|
||||
'^phc@[a-f0-9]+$':
|
||||
$ref: /schemas/ptp/fsl,ptp.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- cell-index
|
||||
- reg
|
||||
- ranges
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- fsl,qman-channel-range
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
fman@400000 {
|
||||
compatible = "fsl,fman";
|
||||
reg = <0x400000 0x100000>;
|
||||
ranges = <0 0x400000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
clocks = <&fman_clk>;
|
||||
clock-names = "fmanclk";
|
||||
interrupts = <96 IRQ_TYPE_EDGE_FALLING>,
|
||||
<16 IRQ_TYPE_EDGE_FALLING>;
|
||||
fsl,qman-channel-range = <0x40 0xc>;
|
||||
|
||||
muram@0 {
|
||||
compatible = "fsl,fman-muram";
|
||||
reg = <0x0 0x28000>;
|
||||
};
|
||||
|
||||
port@81000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,fman-v2-port-oh";
|
||||
reg = <0x81000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_rx_0x8: port@88000 {
|
||||
cell-index = <0x8>;
|
||||
compatible = "fsl,fman-v2-port-rx";
|
||||
reg = <0x88000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_tx_0x28: port@a8000 {
|
||||
cell-index = <0x28>;
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xa8000 0x1000>;
|
||||
};
|
||||
|
||||
ethernet@e0000 {
|
||||
compatible = "fsl,fman-dtsec";
|
||||
cell-index = <0>;
|
||||
reg = <0xe0000 0x1000>;
|
||||
ptp-timer = <&ptp_timer>;
|
||||
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
|
||||
tbi-handle = <&tbi5>;
|
||||
};
|
||||
|
||||
ptp_timer: phc@fe000 {
|
||||
compatible = "fsl,fman-ptp-timer";
|
||||
reg = <0xfe000 0x1000>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
mdio@f1000 {
|
||||
compatible = "fsl,fman-xmdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
interrupts = <101 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,548 +0,0 @@
|
|||
=============================================================================
|
||||
Freescale Frame Manager Device Bindings
|
||||
|
||||
CONTENTS
|
||||
- FMan Node
|
||||
- FMan Port Node
|
||||
- FMan MURAM Node
|
||||
- FMan dTSEC/XGEC/mEMAC Node
|
||||
- FMan IEEE 1588 Node
|
||||
- FMan MDIO Node
|
||||
- Example
|
||||
|
||||
=============================================================================
|
||||
FMan Node
|
||||
|
||||
DESCRIPTION
|
||||
|
||||
Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
|
||||
etc.) the FMan node will have child nodes for each of them.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include "fsl,fman"
|
||||
FMan version can be determined via FM_IP_REV_1 register in the
|
||||
FMan block. The offset is 0xc4 from the beginning of the
|
||||
Frame Processing Manager memory map (0xc3000 from the
|
||||
beginning of the FMan node).
|
||||
|
||||
- cell-index
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: Specifies the index of the FMan unit.
|
||||
|
||||
The cell-index value may be used by the SoC, to identify the
|
||||
FMan unit in the SoC memory map. In the table below,
|
||||
there's a description of the cell-index use in each SoC:
|
||||
|
||||
- P1023:
|
||||
register[bit] FMan unit cell-index
|
||||
============================================================
|
||||
DEVDISR[1] 1 0
|
||||
|
||||
- P2041, P3041, P4080 P5020, P5040:
|
||||
register[bit] FMan unit cell-index
|
||||
============================================================
|
||||
DCFG_DEVDISR2[6] 1 0
|
||||
DCFG_DEVDISR2[14] 2 1
|
||||
(Second FM available only in P4080 and P5040)
|
||||
|
||||
- B4860, T1040, T2080, T4240:
|
||||
register[bit] FMan unit cell-index
|
||||
============================================================
|
||||
DCFG_CCSR_DEVDISR2[24] 1 0
|
||||
DCFG_CCSR_DEVDISR2[25] 2 1
|
||||
(Second FM available only in T4240)
|
||||
|
||||
DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
|
||||
the specific SoC "Device Configuration/Pin Control" Memory
|
||||
Map.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property. Specifies the offset of the
|
||||
following configuration registers:
|
||||
- BMI configuration registers.
|
||||
- QMI configuration registers.
|
||||
- DMA configuration registers.
|
||||
- FPM configuration registers.
|
||||
- FMan controller configuration registers.
|
||||
|
||||
- ranges
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property.
|
||||
|
||||
- clocks
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: phandle for the fman input clock.
|
||||
|
||||
- clock-names
|
||||
usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: "fmanclk" for the fman input clock.
|
||||
|
||||
- interrupts
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A pair of IRQs are specified in this property.
|
||||
The first element is associated with the event interrupts and
|
||||
the second element is associated with the error interrupts.
|
||||
|
||||
- fsl,qman-channel-range
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Specifies the range of the available dedicated
|
||||
channels in the FMan. The first cell specifies the beginning
|
||||
of the range and the second cell specifies the number of
|
||||
channels.
|
||||
Further information available at:
|
||||
"Work Queue (WQ) Channel Assignments in the QMan" section
|
||||
in DPAA Reference Manual.
|
||||
|
||||
- fsl,qman
|
||||
- fsl,bman
|
||||
Usage: required
|
||||
Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
|
||||
|
||||
- fsl,erratum-a050385
|
||||
Usage: optional
|
||||
Value type: boolean
|
||||
Definition: A boolean property. Indicates the presence of the
|
||||
erratum A050385 which indicates that DMA transactions that are
|
||||
split can result in a FMan lock.
|
||||
|
||||
=============================================================================
|
||||
FMan MURAM Node
|
||||
|
||||
DESCRIPTION
|
||||
|
||||
FMan Internal memory - shared between all the FMan modules.
|
||||
It contains data structures that are common and written to or read by
|
||||
the modules.
|
||||
FMan internal memory is split into the following parts:
|
||||
Packet buffering (Tx/Rx FIFOs)
|
||||
Frames internal context
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include "fsl,fman-muram"
|
||||
|
||||
- ranges
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property.
|
||||
Specifies the multi-user memory offset and the size within
|
||||
the FMan.
|
||||
|
||||
EXAMPLE
|
||||
|
||||
muram@0 {
|
||||
compatible = "fsl,fman-muram";
|
||||
ranges = <0 0x000000 0x28000>;
|
||||
};
|
||||
|
||||
=============================================================================
|
||||
FMan Port Node
|
||||
|
||||
DESCRIPTION
|
||||
|
||||
The Frame Manager (FMan) supports several types of hardware ports:
|
||||
Ethernet receiver (RX)
|
||||
Ethernet transmitter (TX)
|
||||
Offline/Host command (O/H)
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: A standard property.
|
||||
Must include one of the following:
|
||||
- "fsl,fman-v2-port-oh" for FManV2 OH ports
|
||||
- "fsl,fman-v2-port-rx" for FManV2 RX ports
|
||||
- "fsl,fman-v2-port-tx" for FManV2 TX ports
|
||||
- "fsl,fman-v3-port-oh" for FManV3 OH ports
|
||||
- "fsl,fman-v3-port-rx" for FManV3 RX ports
|
||||
- "fsl,fman-v3-port-tx" for FManV3 TX ports
|
||||
|
||||
- cell-index
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: Specifies the hardware port id.
|
||||
Each hardware port on the FMan has its own hardware PortID.
|
||||
Super set of all hardware Port IDs available at FMan Reference
|
||||
Manual under "FMan Hardware Ports in Freescale Devices" table.
|
||||
|
||||
Each hardware port is assigned a 4KB, port-specific page in
|
||||
the FMan hardware port memory region (which is part of the
|
||||
FMan memory map). The first 4 KB in the FMan hardware ports
|
||||
memory region is used for what are called common registers.
|
||||
The subsequent 63 4KB pages are allocated to the hardware
|
||||
ports.
|
||||
The page of a specific port is determined by the cell-index.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: There is one reg region describing the port
|
||||
configuration registers.
|
||||
|
||||
- fsl,fman-10g-port
|
||||
Usage: optional
|
||||
Value type: boolean
|
||||
Definition: The default port rate is 1G.
|
||||
If this property exists, the port is s 10G port.
|
||||
|
||||
- fsl,fman-best-effort-port
|
||||
Usage: optional
|
||||
Value type: boolean
|
||||
Definition: Can be defined only if 10G-support is set.
|
||||
This property marks a best-effort 10G port (10G port that
|
||||
may not be capable of line rate).
|
||||
|
||||
EXAMPLE
|
||||
|
||||
port@a8000 {
|
||||
cell-index = <0x28>;
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xa8000 0x1000>;
|
||||
};
|
||||
|
||||
port@88000 {
|
||||
cell-index = <0x8>;
|
||||
compatible = "fsl,fman-v2-port-rx";
|
||||
reg = <0x88000 0x1000>;
|
||||
};
|
||||
|
||||
port@81000 {
|
||||
cell-index = <0x1>;
|
||||
compatible = "fsl,fman-v2-port-oh";
|
||||
reg = <0x81000 0x1000>;
|
||||
};
|
||||
|
||||
=============================================================================
|
||||
FMan dTSEC/XGEC/mEMAC Node
|
||||
|
||||
Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
|
||||
|
||||
============================================================================
|
||||
FMan IEEE 1588 Node
|
||||
|
||||
Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
|
||||
|
||||
=============================================================================
|
||||
FMan MDIO Node
|
||||
|
||||
DESCRIPTION
|
||||
|
||||
The MDIO is a bus to which the PHY devices are connected.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: A standard property.
|
||||
Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
|
||||
Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
|
||||
Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
|
||||
FMan v3.
|
||||
|
||||
- reg
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: A standard property.
|
||||
|
||||
- clocks
|
||||
Usage: optional
|
||||
Value type: <phandle>
|
||||
Definition: A reference to the input clock of the controller
|
||||
from which the MDC frequency is derived.
|
||||
|
||||
- clock-frequency
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Specifies the external MDC frequency, in Hertz, to
|
||||
be used. Requires that the input clock is specified in the
|
||||
"clocks" property. See also: mdio.yaml.
|
||||
|
||||
- suppress-preamble
|
||||
Usage: optional
|
||||
Value type: <boolean>
|
||||
Definition: Disable generation of preamble bits. See also:
|
||||
mdio.yaml.
|
||||
|
||||
- interrupts
|
||||
Usage: required for external MDIO
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Event interrupt of external MDIO controller.
|
||||
|
||||
- fsl,fman-internal-mdio
|
||||
Usage: required for internal MDIO
|
||||
Value type: boolean
|
||||
Definition: Fman has internal MDIO for internal PCS(Physical
|
||||
Coding Sublayer) PHYs and external MDIO for external PHYs.
|
||||
The settings and programming routines for internal/external
|
||||
MDIO are different. Must be included for internal MDIO.
|
||||
|
||||
- fsl,erratum-a009885
|
||||
Usage: optional
|
||||
Value type: <boolean>
|
||||
Definition: Indicates the presence of the A009885
|
||||
erratum describing that the contents of MDIO_DATA may
|
||||
become corrupt unless it is read within 16 MDC cycles
|
||||
of MDIO_CFG[BSY] being cleared, when performing an
|
||||
MDIO read operation.
|
||||
|
||||
- fsl,erratum-a011043
|
||||
Usage: optional
|
||||
Value type: <boolean>
|
||||
Definition: Indicates the presence of the A011043 erratum
|
||||
describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
|
||||
set when reading internal PCS registers. MDIO reads to
|
||||
internal PCS registers may result in having the
|
||||
MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
|
||||
read data (MDIO_DATA[MDIO_DATA]) is correct.
|
||||
Software may get false read error when reading internal
|
||||
PCS registers through MDIO. As a workaround, all internal
|
||||
MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
|
||||
|
||||
For internal PHY device on internal mdio bus, a PHY node should be created.
|
||||
See the definition of the PHY node in booting-without-of.txt for an
|
||||
example of how to define a PHY (Internal PHY has no interrupt line).
|
||||
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
|
||||
- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
|
||||
The PCS PHY address should correspond to the value of the appropriate
|
||||
MDEV_PORT.
|
||||
|
||||
EXAMPLE
|
||||
|
||||
Example for FMan v2 external MDIO:
|
||||
|
||||
mdio@f1000 {
|
||||
compatible = "fsl,fman-xmdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
interrupts = <101 2 0 0>;
|
||||
};
|
||||
|
||||
Example for FMan v2 internal MDIO:
|
||||
|
||||
mdio@e3120 {
|
||||
compatible = "fsl,fman-mdio";
|
||||
reg = <0xe3120 0xee0>;
|
||||
fsl,fman-internal-mdio;
|
||||
|
||||
tbi1: tbi-phy@8 {
|
||||
reg = <0x8>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
Example for FMan v3 internal MDIO:
|
||||
|
||||
mdio@f1000 {
|
||||
compatible = "fsl,fman-memac-mdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
fsl,fman-internal-mdio;
|
||||
|
||||
pcsphy6: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
=============================================================================
|
||||
Example
|
||||
|
||||
fman@400000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,fman"
|
||||
ranges = <0 0x400000 0x100000>;
|
||||
reg = <0x400000 0x100000>;
|
||||
clocks = <&fman_clk>;
|
||||
clock-names = "fmanclk";
|
||||
interrupts = <
|
||||
96 2 0 0
|
||||
16 2 1 1>;
|
||||
fsl,qman-channel-range = <0x40 0xc>;
|
||||
|
||||
muram@0 {
|
||||
compatible = "fsl,fman-muram";
|
||||
reg = <0x0 0x28000>;
|
||||
};
|
||||
|
||||
port@81000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,fman-v2-port-oh";
|
||||
reg = <0x81000 0x1000>;
|
||||
};
|
||||
|
||||
port@82000 {
|
||||
cell-index = <2>;
|
||||
compatible = "fsl,fman-v2-port-oh";
|
||||
reg = <0x82000 0x1000>;
|
||||
};
|
||||
|
||||
port@83000 {
|
||||
cell-index = <3>;
|
||||
compatible = "fsl,fman-v2-port-oh";
|
||||
reg = <0x83000 0x1000>;
|
||||
};
|
||||
|
||||
port@84000 {
|
||||
cell-index = <4>;
|
||||
compatible = "fsl,fman-v2-port-oh";
|
||||
reg = <0x84000 0x1000>;
|
||||
};
|
||||
|
||||
port@85000 {
|
||||
cell-index = <5>;
|
||||
compatible = "fsl,fman-v2-port-oh";
|
||||
reg = <0x85000 0x1000>;
|
||||
};
|
||||
|
||||
port@86000 {
|
||||
cell-index = <6>;
|
||||
compatible = "fsl,fman-v2-port-oh";
|
||||
reg = <0x86000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_rx_0x8: port@88000 {
|
||||
cell-index = <0x8>;
|
||||
compatible = "fsl,fman-v2-port-rx";
|
||||
reg = <0x88000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_rx_0x9: port@89000 {
|
||||
cell-index = <0x9>;
|
||||
compatible = "fsl,fman-v2-port-rx";
|
||||
reg = <0x89000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_rx_0xa: port@8a000 {
|
||||
cell-index = <0xa>;
|
||||
compatible = "fsl,fman-v2-port-rx";
|
||||
reg = <0x8a000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_rx_0xb: port@8b000 {
|
||||
cell-index = <0xb>;
|
||||
compatible = "fsl,fman-v2-port-rx";
|
||||
reg = <0x8b000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_rx_0xc: port@8c000 {
|
||||
cell-index = <0xc>;
|
||||
compatible = "fsl,fman-v2-port-rx";
|
||||
reg = <0x8c000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_rx_0x10: port@90000 {
|
||||
cell-index = <0x10>;
|
||||
compatible = "fsl,fman-v2-port-rx";
|
||||
reg = <0x90000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_tx_0x28: port@a8000 {
|
||||
cell-index = <0x28>;
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xa8000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_tx_0x29: port@a9000 {
|
||||
cell-index = <0x29>;
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xa9000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_tx_0x2a: port@aa000 {
|
||||
cell-index = <0x2a>;
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xaa000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_tx_0x2b: port@ab000 {
|
||||
cell-index = <0x2b>;
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xab000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_tx_0x2c: port@ac0000 {
|
||||
cell-index = <0x2c>;
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xac000 0x1000>;
|
||||
};
|
||||
|
||||
fman1_tx_0x30: port@b0000 {
|
||||
cell-index = <0x30>;
|
||||
compatible = "fsl,fman-v2-port-tx";
|
||||
reg = <0xb0000 0x1000>;
|
||||
};
|
||||
|
||||
ethernet@e0000 {
|
||||
compatible = "fsl,fman-dtsec";
|
||||
cell-index = <0>;
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
|
||||
tbi-handle = <&tbi5>;
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
compatible = "fsl,fman-dtsec";
|
||||
cell-index = <1>;
|
||||
reg = <0xe2000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
|
||||
tbi-handle = <&tbi6>;
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
compatible = "fsl,fman-dtsec";
|
||||
cell-index = <2>;
|
||||
reg = <0xe4000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
|
||||
tbi-handle = <&tbi7>;
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
compatible = "fsl,fman-dtsec";
|
||||
cell-index = <3>;
|
||||
reg = <0xe6000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
|
||||
tbi-handle = <&tbi8>;
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
compatible = "fsl,fman-dtsec";
|
||||
cell-index = <4>;
|
||||
reg = <0xf0000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
|
||||
tbi-handle = <&tbi9>;
|
||||
|
||||
ethernet@f0000 {
|
||||
cell-index = <8>;
|
||||
compatible = "fsl,fman-xgec";
|
||||
reg = <0xf0000 0x1000>;
|
||||
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
|
||||
};
|
||||
|
||||
ptp-timer@fe000 {
|
||||
compatible = "fsl,fman-ptp-timer";
|
||||
reg = <0xfe000 0x1000>;
|
||||
};
|
||||
|
||||
mdio@f1000 {
|
||||
compatible = "fsl,fman-xmdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
interrupts = <101 2 0 0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -86,4 +86,4 @@ Example:
|
|||
|
||||
* Gianfar PTP clock nodes
|
||||
|
||||
Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
|
||||
Refer to Documentation/devicetree/bindings/ptp/fsl,ptp.yaml
|
||||
|
|
|
|||
144
Documentation/devicetree/bindings/ptp/fsl,ptp.yaml
Normal file
144
Documentation/devicetree/bindings/ptp/fsl,ptp.yaml
Normal file
|
|
@ -0,0 +1,144 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ptp/fsl,ptp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale QorIQ 1588 timer based PTP clock
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,etsec-ptp
|
||||
- fsl,fman-ptp-timer
|
||||
- fsl,dpaa2-ptp
|
||||
- fsl,enetc-ptp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
fsl,cksel:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Timer reference clock source.
|
||||
|
||||
Reference clock source is determined by the value, which is holded
|
||||
in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
|
||||
value, which will be directly written in those bits, that is why,
|
||||
according to reference manual, the next clock sources can be used:
|
||||
|
||||
For eTSEC,
|
||||
<0> - external high precision timer reference clock (TSEC_TMR_CLK
|
||||
input is used for this purpose);
|
||||
<1> - eTSEC system clock;
|
||||
<2> - eTSEC1 transmit clock;
|
||||
<3> - RTC clock input.
|
||||
|
||||
For DPAA FMan,
|
||||
<0> - external high precision timer reference clock (TMR_1588_CLK)
|
||||
<1> - MAC system clock (1/2 FMan clock)
|
||||
<2> - reserved
|
||||
<3> - RTC clock oscillator
|
||||
|
||||
fsl,tclk-period:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Timer reference clock period in nanoseconds.
|
||||
|
||||
fsl,tmr-prsc:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Prescaler, divides the output clock.
|
||||
|
||||
fsl,tmr-add:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Frequency compensation value.
|
||||
|
||||
fsl,tmr-fiper1:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Fixed interval period pulse generator.
|
||||
|
||||
fsl,tmr-fiper2:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Fixed interval period pulse generator.
|
||||
|
||||
fsl,tmr-fiper3:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Fixed interval period pulse generator.
|
||||
Supported only on DPAA2 and ENETC hardware.
|
||||
|
||||
fsl,max-adj:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Maximum frequency adjustment in parts per billion.
|
||||
|
||||
These properties set the operational parameters for the PTP
|
||||
clock. You must choose these carefully for the clock to work right.
|
||||
Here is how to figure good values:
|
||||
|
||||
TimerOsc = selected reference clock MHz
|
||||
tclk_period = desired clock period nanoseconds
|
||||
NominalFreq = 1000 / tclk_period MHz
|
||||
FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
|
||||
tmr_add = ceil(2^32 / FreqDivRatio)
|
||||
OutputClock = NominalFreq / tmr_prsc MHz
|
||||
PulseWidth = 1 / OutputClock microseconds
|
||||
FiperFreq1 = desired frequency in Hz
|
||||
FiperDiv1 = 1000000 * OutputClock / FiperFreq1
|
||||
tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
|
||||
max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
|
||||
|
||||
The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
|
||||
driver expects that tmr_fiper1 will be correctly set to produce a 1
|
||||
Pulse Per Second (PPS) signal, since this will be offered to the PPS
|
||||
subsystem to synchronize the Linux clock.
|
||||
|
||||
When this attribute is not used, the IEEE 1588 timer reference clock
|
||||
will use the eTSEC system clock (for Gianfar) or the MAC system
|
||||
clock (for DPAA).
|
||||
|
||||
fsl,extts-fifo:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The presence of this property indicates hardware
|
||||
support for the external trigger stamp FIFO
|
||||
|
||||
little-endian:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
The presence of this property indicates the 1588 timer
|
||||
support for the external trigger stamp FIFO.
|
||||
IP block is little-endian mode. The default endian mode
|
||||
is big-endian.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
phc@24e00 {
|
||||
compatible = "fsl,etsec-ptp";
|
||||
reg = <0x24e00 0xb0>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-parent = <&ipic>;
|
||||
fsl,cksel = <1>;
|
||||
fsl,tclk-period = <10>;
|
||||
fsl,tmr-prsc = <100>;
|
||||
fsl,tmr-add = <0x999999a4>;
|
||||
fsl,tmr-fiper1 = <0x3b9ac9f6>;
|
||||
fsl,tmr-fiper2 = <0x00018696>;
|
||||
fsl,max-adj = <659999998>;
|
||||
};
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
* Freescale QorIQ 1588 timer based PTP clock
|
||||
|
||||
General Properties:
|
||||
|
||||
- compatible Should be "fsl,etsec-ptp" for eTSEC
|
||||
Should be "fsl,fman-ptp-timer" for DPAA FMan
|
||||
Should be "fsl,dpaa2-ptp" for DPAA2
|
||||
Should be "fsl,enetc-ptp" for ENETC
|
||||
- reg Offset and length of the register set for the device
|
||||
- interrupts There should be at least two interrupts. Some devices
|
||||
have as many as four PTP related interrupts.
|
||||
|
||||
Clock Properties:
|
||||
|
||||
- fsl,cksel Timer reference clock source.
|
||||
- fsl,tclk-period Timer reference clock period in nanoseconds.
|
||||
- fsl,tmr-prsc Prescaler, divides the output clock.
|
||||
- fsl,tmr-add Frequency compensation value.
|
||||
- fsl,tmr-fiper1 Fixed interval period pulse generator.
|
||||
- fsl,tmr-fiper2 Fixed interval period pulse generator.
|
||||
- fsl,tmr-fiper3 Fixed interval period pulse generator.
|
||||
Supported only on DPAA2 and ENETC hardware.
|
||||
- fsl,max-adj Maximum frequency adjustment in parts per billion.
|
||||
- fsl,extts-fifo The presence of this property indicates hardware
|
||||
support for the external trigger stamp FIFO.
|
||||
- little-endian The presence of this property indicates the 1588 timer
|
||||
IP block is little-endian mode. The default endian mode
|
||||
is big-endian.
|
||||
|
||||
These properties set the operational parameters for the PTP
|
||||
clock. You must choose these carefully for the clock to work right.
|
||||
Here is how to figure good values:
|
||||
|
||||
TimerOsc = selected reference clock MHz
|
||||
tclk_period = desired clock period nanoseconds
|
||||
NominalFreq = 1000 / tclk_period MHz
|
||||
FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
|
||||
tmr_add = ceil(2^32 / FreqDivRatio)
|
||||
OutputClock = NominalFreq / tmr_prsc MHz
|
||||
PulseWidth = 1 / OutputClock microseconds
|
||||
FiperFreq1 = desired frequency in Hz
|
||||
FiperDiv1 = 1000000 * OutputClock / FiperFreq1
|
||||
tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
|
||||
max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
|
||||
|
||||
The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
|
||||
driver expects that tmr_fiper1 will be correctly set to produce a 1
|
||||
Pulse Per Second (PPS) signal, since this will be offered to the PPS
|
||||
subsystem to synchronize the Linux clock.
|
||||
|
||||
Reference clock source is determined by the value, which is holded
|
||||
in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
|
||||
value, which will be directly written in those bits, that is why,
|
||||
according to reference manual, the next clock sources can be used:
|
||||
|
||||
For eTSEC,
|
||||
<0> - external high precision timer reference clock (TSEC_TMR_CLK
|
||||
input is used for this purpose);
|
||||
<1> - eTSEC system clock;
|
||||
<2> - eTSEC1 transmit clock;
|
||||
<3> - RTC clock input.
|
||||
|
||||
For DPAA FMan,
|
||||
<0> - external high precision timer reference clock (TMR_1588_CLK)
|
||||
<1> - MAC system clock (1/2 FMan clock)
|
||||
<2> - reserved
|
||||
<3> - RTC clock oscillator
|
||||
|
||||
When this attribute is not used, the IEEE 1588 timer reference clock
|
||||
will use the eTSEC system clock (for Gianfar) or the MAC system
|
||||
clock (for DPAA).
|
||||
|
||||
Example:
|
||||
|
||||
ptp_clock@24e00 {
|
||||
compatible = "fsl,etsec-ptp";
|
||||
reg = <0x24E00 0xB0>;
|
||||
interrupts = <12 0x8 13 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
fsl,cksel = <1>;
|
||||
fsl,tclk-period = <10>;
|
||||
fsl,tmr-prsc = <100>;
|
||||
fsl,tmr-add = <0x999999A4>;
|
||||
fsl,tmr-fiper1 = <0x3B9AC9F6>;
|
||||
fsl,tmr-fiper2 = <0x00018696>;
|
||||
fsl,max-adj = <659999998>;
|
||||
};
|
||||
|
|
@ -8809,14 +8809,14 @@ M: Madalin Bucur <madalin.bucur@nxp.com>
|
|||
R: Sean Anderson <sean.anderson@seco.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/net/fsl-fman.txt
|
||||
F: Documentation/devicetree/bindings/net/fsl-fman.yaml
|
||||
F: drivers/net/ethernet/freescale/fman
|
||||
|
||||
FREESCALE QORIQ PTP CLOCK DRIVER
|
||||
M: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
|
||||
F: Documentation/devicetree/bindings/ptp/fsl,ptp.yaml
|
||||
F: drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp*
|
||||
F: drivers/net/ethernet/freescale/dpaa2/dprtc*
|
||||
F: drivers/net/ethernet/freescale/enetc/enetc_ptp.c
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user