RISC-V SoC drivers for v6.2

SiFive:
 - add probe error handling to the ccache driver
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Merge tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers

RISC-V SoC drivers for v6.2

SiFive:
- add probe error handling to the ccache driver

* tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()
  soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
  soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()

Link: https://lore.kernel.org/r/Y3u0Oydiv2Wauda2@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-11-22 15:27:59 +01:00
commit 862fe29b89

View File

@ -215,20 +215,27 @@ static int __init sifive_ccache_init(void)
if (!np)
return -ENODEV;
if (of_address_to_resource(np, 0, &res))
return -ENODEV;
if (of_address_to_resource(np, 0, &res)) {
rc = -ENODEV;
goto err_node_put;
}
ccache_base = ioremap(res.start, resource_size(&res));
if (!ccache_base)
return -ENOMEM;
if (!ccache_base) {
rc = -ENOMEM;
goto err_node_put;
}
if (of_property_read_u32(np, "cache-level", &level))
return -ENOENT;
if (of_property_read_u32(np, "cache-level", &level)) {
rc = -ENOENT;
goto err_unmap;
}
intr_num = of_property_count_u32_elems(np, "interrupts");
if (!intr_num) {
pr_err("No interrupts property\n");
return -ENODEV;
rc = -ENODEV;
goto err_unmap;
}
for (i = 0; i < intr_num; i++) {
@ -237,9 +244,10 @@ static int __init sifive_ccache_init(void)
NULL);
if (rc) {
pr_err("Could not request IRQ %d\n", g_irq[i]);
return rc;
goto err_free_irq;
}
}
of_node_put(np);
ccache_config_read();
@ -250,6 +258,15 @@ static int __init sifive_ccache_init(void)
setup_sifive_debug();
#endif
return 0;
err_free_irq:
while (--i >= 0)
free_irq(g_irq[i], NULL);
err_unmap:
iounmap(ccache_base);
err_node_put:
of_node_put(np);
return rc;
}
device_initcall(sifive_ccache_init);