spi: spi-mem: Limit octal DTR constraints to octal DTR situations

In this helper, any operation with a single DTR cycle (like 1S-1S-8D) is
considered requiring a duplicated command opcode. This is wrong as this
constraint only applies to octal DTR operations (8D-8D-8D).

Narrow the application of this constraint to the concerned bus
interface.

Note: none of the possible XD-XD-XD pattern, with X being one of {1, 2,
4} would benefit from this check either as there is only in octal DTR
mode that a single clock edge would be enough to transmit the full
opcode.

Make sure the constraint of expecting two bytes for the command is
applied to the relevant bus interface.

Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260109-winbond-v6-17-rc1-oddr-v2-3-1fff6a2ddb80@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Miquel Raynal 2026-01-09 18:18:01 +01:00 committed by Mark Brown
parent af4b2dc481
commit 8618271887
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@ -178,8 +178,19 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
if (op->data.swap16 && !spi_mem_controller_is_capable(ctlr, swap16))
return false;
if (op->cmd.nbytes != 2)
return false;
/* Extra 8D-8D-8D limitations */
if (op->cmd.dtr && op->cmd.buswidth == 8) {
if (op->cmd.nbytes != 2)
return false;
if ((op->addr.nbytes % 2) ||
(op->dummy.nbytes % 2) ||
(op->data.nbytes % 2)) {
dev_err(&ctlr->dev,
"Even byte numbers not allowed in octal DTR operations\n");
return false;
}
}
} else {
if (op->cmd.nbytes != 1)
return false;