mirror of
https://github.com/torvalds/linux.git
synced 2026-05-23 14:42:08 +02:00
pinctrl: renesas: Updates for v6.4 (take two)
- Retain POCCTRL0 register across s2ram on R-Car D3,
- Add support for Ethernet power-sources on R-Car V3M, V3H, E3, D3,
and V4H,
- Annotate sentinels in tables,
- Add bias pinconf support and PWM pin groups on R-Car H1,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.4 (take two)
- Retain POCCTRL0 register across s2ram on R-Car D3,
- Add support for Ethernet power-sources on R-Car V3M, V3H, E3, D3,
and V4H,
- Annotate sentinels in tables,
- Add bias pinconf support and PWM pin groups on R-Car H1,
- Miscellaneous fixes and improvements.
This commit is contained in:
Linus Walleij
commit
86169e657a
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@ -645,7 +645,7 @@ static const struct of_device_id sh_pfc_of_table[] = {
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.data = &sh73a0_pinmux_info,
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},
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#endif
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{ },
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{ /* sentinel */ }
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};
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#endif
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@ -1114,9 +1114,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
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}
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}
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if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
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if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK) {
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if (!info->ops || !info->ops->pin_to_pocctrl)
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sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
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sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE set but .pin_to_pocctrl() not implemented\n");
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else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
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sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
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pin->name);
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@ -1304,11 +1304,9 @@ static int sh_pfc_probe(struct platform_device *pdev)
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struct sh_pfc *pfc;
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int ret;
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#ifdef CONFIG_OF
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if (pdev->dev.of_node)
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info = of_device_get_match_data(&pdev->dev);
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else
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#endif
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info = (const void *)platform_get_device_id(pdev)->driver_data;
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pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
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@ -1411,7 +1409,7 @@ static const struct platform_device_id sh_pfc_id_table[] = {
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#ifdef CONFIG_PINCTRL_PFC_SHX3
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{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
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#endif
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{ },
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{ /* sentinel */ }
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};
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static struct platform_driver sh_pfc_driver = {
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@ -1644,7 +1644,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
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))
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},
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{ },
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{ /* sentinel */ }
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};
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const struct sh_pfc_soc_info emev2_pinmux_info = {
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@ -2384,7 +2384,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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MSEL8CR_00_0, MSEL8CR_00_1,
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))
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},
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{ },
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{ /* sentinel */ }
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};
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static const struct pinmux_data_reg pinmux_data_regs[] = {
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@ -2510,7 +2510,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
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))
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},
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{ },
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{ /* sentinel */ }
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};
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static const struct pinmux_irq pinmux_irqs[] = {
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@ -3348,7 +3348,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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MSEL5CR_0_0, MSEL5CR_0_1,
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))
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},
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{ },
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{ /* sentinel */ }
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};
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static const struct pinmux_data_reg pinmux_data_regs[] = {
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@ -3452,7 +3452,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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0, 0, 0, 0,
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0, 0, 0, 0 ))
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},
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{ },
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{ /* sentinel */ }
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};
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static const struct pinmux_irq pinmux_irqs[] = {
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@ -13,24 +13,24 @@
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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@ -38,12 +38,12 @@
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PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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@ -3252,7 +3252,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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/* SEL_SSI0 [2] */
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FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
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},
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{ },
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{ /* sentinel */ }
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};
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static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
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|
|
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@ -2832,7 +2832,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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FN_SEL_I2C1_A, FN_SEL_I2C1_B,
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))
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},
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{ },
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{ /* sentinel */ }
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};
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static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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@ -3040,7 +3040,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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[30] = SH_PFC_PIN_NONE,
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[31] = SH_PFC_PIN_NONE,
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} },
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{ /* sentinel */ },
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{ /* sentinel */ }
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};
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static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
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|
|
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|
|
@ -12,13 +12,76 @@
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#include "sh_pfc.h"
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|
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#define CPU_ALL_GP(fn, sfx) \
|
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PORT_GP_32(0, fn, sfx), \
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PORT_GP_32(1, fn, sfx), \
|
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PORT_GP_32(2, fn, sfx), \
|
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PORT_GP_32(3, fn, sfx), \
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PORT_GP_32(4, fn, sfx), \
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PORT_GP_32(5, fn, sfx), \
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PORT_GP_9(6, fn, sfx)
|
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PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
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PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
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PORT_GP_CFG_1(2, 0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
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PORT_GP_1(2, 1, fn, sfx), \
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PORT_GP_1(2, 2, fn, sfx), \
|
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PORT_GP_1(2, 3, fn, sfx), \
|
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PORT_GP_1(2, 4, fn, sfx), \
|
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PORT_GP_1(2, 5, fn, sfx), \
|
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PORT_GP_1(2, 6, fn, sfx), \
|
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PORT_GP_1(2, 7, fn, sfx), \
|
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PORT_GP_1(2, 8, fn, sfx), \
|
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PORT_GP_1(2, 9, fn, sfx), \
|
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PORT_GP_1(2, 10, fn, sfx), \
|
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PORT_GP_1(2, 11, fn, sfx), \
|
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PORT_GP_1(2, 12, fn, sfx), \
|
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PORT_GP_1(2, 13, fn, sfx), \
|
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PORT_GP_1(2, 14, fn, sfx), \
|
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PORT_GP_1(2, 15, fn, sfx), \
|
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PORT_GP_1(2, 16, fn, sfx), \
|
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PORT_GP_1(2, 17, fn, sfx), \
|
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PORT_GP_1(2, 18, fn, sfx), \
|
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PORT_GP_1(2, 19, fn, sfx), \
|
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PORT_GP_1(2, 20, fn, sfx), \
|
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PORT_GP_1(2, 21, fn, sfx), \
|
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PORT_GP_1(2, 22, fn, sfx), \
|
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PORT_GP_1(2, 23, fn, sfx), \
|
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PORT_GP_1(2, 24, fn, sfx), \
|
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PORT_GP_1(2, 25, fn, sfx), \
|
||||
PORT_GP_1(2, 26, fn, sfx), \
|
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PORT_GP_1(2, 27, fn, sfx), \
|
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PORT_GP_1(2, 28, fn, sfx), \
|
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PORT_GP_1(2, 29, fn, sfx), \
|
||||
PORT_GP_CFG_1(2, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
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PORT_GP_CFG_1(2, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
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PORT_GP_CFG_25(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
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PORT_GP_1(3, 25, fn, sfx), \
|
||||
PORT_GP_1(3, 26, fn, sfx), \
|
||||
PORT_GP_1(3, 27, fn, sfx), \
|
||||
PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(3, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(3, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_9(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D0, "D0", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D1, "D1", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D2, "D2", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D3, "D3", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D4, "D4", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D5, "D5", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D6, "D6", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D7, "D7", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D8, "D8", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D9, "D9", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D10, "D10", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D11, "D11", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D12, "D12", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D13, "D13", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D14, "D14", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(D15, "D15", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
enum {
|
||||
PINMUX_RESERVED = 0,
|
||||
|
|
@ -1390,8 +1453,17 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
|
||||
};
|
||||
|
||||
/*
|
||||
* Pins not associated with a GPIO port.
|
||||
*/
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - DU0 -------------------------------------------------------------------- */
|
||||
|
|
@ -1962,6 +2034,67 @@ static const unsigned int mmc1_ctrl_pins[] = {
|
|||
static const unsigned int mmc1_ctrl_mux[] = {
|
||||
MMC1_CMD_MARK, MMC1_CLK_MARK,
|
||||
};
|
||||
/* - PWM -------------------------------------------------------------------- */
|
||||
static const unsigned int pwm0_pins[] = {
|
||||
RCAR_GP_PIN(1, 3),
|
||||
};
|
||||
static const unsigned int pwm0_mux[] = {
|
||||
PWM0_MARK,
|
||||
};
|
||||
static const unsigned int pwm0_b_pins[] = {
|
||||
RCAR_GP_PIN(0, 12),
|
||||
};
|
||||
static const unsigned int pwm0_b_mux[] = {
|
||||
PWM0_B_MARK,
|
||||
};
|
||||
static const unsigned int pwm0_c_pins[] = {
|
||||
RCAR_GP_PIN(4, 5),
|
||||
};
|
||||
static const unsigned int pwm0_c_mux[] = {
|
||||
PWM0_C_MARK,
|
||||
};
|
||||
static const unsigned int pwm0_d_pins[] = {
|
||||
RCAR_GP_PIN(4, 18),
|
||||
};
|
||||
static const unsigned int pwm0_d_mux[] = {
|
||||
PWM0_D_MARK,
|
||||
};
|
||||
static const unsigned int pwm1_pins[] = {
|
||||
RCAR_GP_PIN(4, 28),
|
||||
};
|
||||
static const unsigned int pwm1_mux[] = {
|
||||
PWM1_MARK,
|
||||
};
|
||||
static const unsigned int pwm2_pins[] = {
|
||||
RCAR_GP_PIN(3, 25),
|
||||
};
|
||||
static const unsigned int pwm2_mux[] = {
|
||||
PWM2_MARK,
|
||||
};
|
||||
static const unsigned int pwm3_pins[] = {
|
||||
RCAR_GP_PIN(3, 26),
|
||||
};
|
||||
static const unsigned int pwm3_mux[] = {
|
||||
PWM3_MARK,
|
||||
};
|
||||
static const unsigned int pwm4_pins[] = {
|
||||
RCAR_GP_PIN(3, 27),
|
||||
};
|
||||
static const unsigned int pwm4_mux[] = {
|
||||
PWM4_MARK,
|
||||
};
|
||||
static const unsigned int pwm5_pins[] = {
|
||||
RCAR_GP_PIN(4, 17),
|
||||
};
|
||||
static const unsigned int pwm5_mux[] = {
|
||||
PWM5_MARK,
|
||||
};
|
||||
static const unsigned int pwm6_pins[] = {
|
||||
RCAR_GP_PIN(1, 2),
|
||||
};
|
||||
static const unsigned int pwm6_mux[] = {
|
||||
PWM6_MARK,
|
||||
};
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_pins[] = {
|
||||
/* RXD, TXD */
|
||||
|
|
@ -2699,6 +2832,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
|||
BUS_DATA_PIN_GROUP(mmc1_data, 4),
|
||||
BUS_DATA_PIN_GROUP(mmc1_data, 8),
|
||||
SH_PFC_PIN_GROUP(mmc1_ctrl),
|
||||
SH_PFC_PIN_GROUP(pwm0),
|
||||
SH_PFC_PIN_GROUP(pwm0_b),
|
||||
SH_PFC_PIN_GROUP(pwm0_c),
|
||||
SH_PFC_PIN_GROUP(pwm0_d),
|
||||
SH_PFC_PIN_GROUP(pwm1),
|
||||
SH_PFC_PIN_GROUP(pwm2),
|
||||
SH_PFC_PIN_GROUP(pwm3),
|
||||
SH_PFC_PIN_GROUP(pwm4),
|
||||
SH_PFC_PIN_GROUP(pwm5),
|
||||
SH_PFC_PIN_GROUP(pwm6),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
SH_PFC_PIN_GROUP(scif0_clk),
|
||||
SH_PFC_PIN_GROUP(scif0_ctrl),
|
||||
|
|
@ -2912,6 +3055,37 @@ static const char * const mmc1_groups[] = {
|
|||
"mmc1_ctrl",
|
||||
};
|
||||
|
||||
static const char * const pwm0_groups[] = {
|
||||
"pwm0",
|
||||
"pwm0_b",
|
||||
"pwm0_c",
|
||||
"pwm0_d",
|
||||
};
|
||||
|
||||
static const char * const pwm1_groups[] = {
|
||||
"pwm1",
|
||||
};
|
||||
|
||||
static const char * const pwm2_groups[] = {
|
||||
"pwm2",
|
||||
};
|
||||
|
||||
static const char * const pwm3_groups[] = {
|
||||
"pwm3",
|
||||
};
|
||||
|
||||
static const char * const pwm4_groups[] = {
|
||||
"pwm4",
|
||||
};
|
||||
|
||||
static const char * const pwm5_groups[] = {
|
||||
"pwm5",
|
||||
};
|
||||
|
||||
static const char * const pwm6_groups[] = {
|
||||
"pwm6",
|
||||
};
|
||||
|
||||
static const char * const scif0_groups[] = {
|
||||
"scif0_data",
|
||||
"scif0_clk",
|
||||
|
|
@ -3075,6 +3249,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
|||
SH_PFC_FUNCTION(lbsc),
|
||||
SH_PFC_FUNCTION(mmc0),
|
||||
SH_PFC_FUNCTION(mmc1),
|
||||
SH_PFC_FUNCTION(pwm0),
|
||||
SH_PFC_FUNCTION(pwm1),
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
SH_PFC_FUNCTION(pwm3),
|
||||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(pwm5),
|
||||
SH_PFC_FUNCTION(pwm6),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
SH_PFC_FUNCTION(scif2),
|
||||
|
|
@ -3919,11 +4100,259 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* SEL_I2C1 [2] */
|
||||
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
{ PINMUX_BIAS_REG("PUPR0", 0xfffc0100, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(0, 2), /* A0 */
|
||||
[ 1] = RCAR_GP_PIN(5, 0), /* A1 */
|
||||
[ 2] = RCAR_GP_PIN(5, 1), /* A2 */
|
||||
[ 3] = RCAR_GP_PIN(5, 2), /* A3 */
|
||||
[ 4] = RCAR_GP_PIN(5, 3), /* A4 */
|
||||
[ 5] = RCAR_GP_PIN(5, 4), /* A5 */
|
||||
[ 6] = RCAR_GP_PIN(5, 5), /* A6 */
|
||||
[ 7] = RCAR_GP_PIN(5, 6), /* A7 */
|
||||
[ 8] = RCAR_GP_PIN(5, 7), /* A8 */
|
||||
[ 9] = RCAR_GP_PIN(5, 8), /* A9 */
|
||||
[10] = RCAR_GP_PIN(5, 9), /* A10 */
|
||||
[11] = RCAR_GP_PIN(5, 10), /* A11 */
|
||||
[12] = RCAR_GP_PIN(5, 11), /* A12 */
|
||||
[13] = RCAR_GP_PIN(5, 12), /* A13 */
|
||||
[14] = RCAR_GP_PIN(5, 13), /* A14 */
|
||||
[15] = RCAR_GP_PIN(5, 14), /* A15 */
|
||||
[16] = RCAR_GP_PIN(5, 15), /* A16 */
|
||||
[17] = RCAR_GP_PIN(0, 3), /* A17 */
|
||||
[18] = RCAR_GP_PIN(0, 4), /* A18 */
|
||||
[19] = RCAR_GP_PIN(0, 5), /* A19 */
|
||||
[20] = RCAR_GP_PIN(0, 6), /* A20 */
|
||||
[21] = RCAR_GP_PIN(0, 7), /* A21 */
|
||||
[22] = RCAR_GP_PIN(0, 8), /* A22 */
|
||||
[23] = RCAR_GP_PIN(0, 9), /* A23 */
|
||||
[24] = RCAR_GP_PIN(0, 10), /* A24 */
|
||||
[25] = RCAR_GP_PIN(0, 11), /* A25 */
|
||||
[26] = RCAR_GP_PIN(0, 15), /* EX_CS0# */
|
||||
[27] = RCAR_GP_PIN(0, 16), /* EX_CS1# */
|
||||
[28] = RCAR_GP_PIN(0, 17), /* EX_CS2# */
|
||||
[29] = RCAR_GP_PIN(0, 18), /* EX_CS3# */
|
||||
[30] = RCAR_GP_PIN(0, 19), /* EX_CS4# */
|
||||
[31] = RCAR_GP_PIN(0, 20), /* EX_CS5# */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR1", 0xfffc0104, "N/A", 0) {
|
||||
[ 0] = PIN_PRESETOUT_N, /* PRESETOUT# */
|
||||
[ 1] = RCAR_GP_PIN(0, 21), /* BS# */
|
||||
[ 2] = RCAR_GP_PIN(0, 22), /* RD/WR# */
|
||||
[ 3] = RCAR_GP_PIN(5, 17), /* WE0# */
|
||||
[ 4] = RCAR_GP_PIN(5, 18), /* WE1# */
|
||||
[ 5] = RCAR_GP_PIN(5, 19), /* EX_WAIT0 */
|
||||
[ 6] = RCAR_GP_PIN(0, 0), /* AVS1 */
|
||||
[ 7] = RCAR_GP_PIN(0, 1), /* AVS2 */
|
||||
[ 8] = SH_PFC_PIN_NONE,
|
||||
[ 9] = SH_PFC_PIN_NONE,
|
||||
[10] = PIN_TRST_N, /* TRST# */
|
||||
[11] = PIN_TCK, /* TCK */
|
||||
[12] = PIN_TMS, /* TMS */
|
||||
[13] = PIN_TDI, /* TDI */
|
||||
[14] = PIN_TDO, /* TDO */
|
||||
[15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
|
||||
[16] = PIN_D0, /* D0 */
|
||||
[17] = PIN_D1, /* D1 */
|
||||
[18] = PIN_D2, /* D2 */
|
||||
[19] = PIN_D3, /* D3 */
|
||||
[20] = PIN_D4, /* D4 */
|
||||
[21] = PIN_D5, /* D5 */
|
||||
[22] = PIN_D6, /* D6 */
|
||||
[23] = PIN_D7, /* D7 */
|
||||
[24] = PIN_D8, /* D8 */
|
||||
[25] = PIN_D9, /* D9 */
|
||||
[26] = PIN_D10, /* D10 */
|
||||
[27] = PIN_D11, /* D11 */
|
||||
[28] = PIN_D12, /* D12 */
|
||||
[29] = PIN_D13, /* D13 */
|
||||
[30] = PIN_D14, /* D14 */
|
||||
[31] = PIN_D15, /* D15 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR2", 0xfffc0108, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(0, 23), /* DU0_DR0 */
|
||||
[ 1] = RCAR_GP_PIN(0, 24), /* DU0_DR1 */
|
||||
[ 2] = RCAR_GP_PIN(5, 23), /* DU0_DR2 */
|
||||
[ 3] = RCAR_GP_PIN(5, 24), /* DU0_DR3 */
|
||||
[ 4] = RCAR_GP_PIN(5, 25), /* DU0_DR4 */
|
||||
[ 5] = RCAR_GP_PIN(5, 26), /* DU0_DR5 */
|
||||
[ 6] = RCAR_GP_PIN(5, 27), /* DU0_DR6 */
|
||||
[ 7] = RCAR_GP_PIN(5, 28), /* DU0_DR7 */
|
||||
[ 8] = RCAR_GP_PIN(0, 25), /* DU0_DG0 */
|
||||
[ 9] = RCAR_GP_PIN(0, 26), /* DU0_DG1 */
|
||||
[10] = RCAR_GP_PIN(5, 29), /* DU0_DG2 */
|
||||
[11] = RCAR_GP_PIN(5, 30), /* DU0_DG3 */
|
||||
[12] = RCAR_GP_PIN(5, 31), /* DU0_DG4 */
|
||||
[13] = RCAR_GP_PIN(6, 0), /* DU0_DG5 */
|
||||
[14] = RCAR_GP_PIN(6, 1), /* DU0_DG6 */
|
||||
[15] = RCAR_GP_PIN(6, 2), /* DU0_DG7 */
|
||||
[16] = RCAR_GP_PIN(0, 27), /* DU0_DB0 */
|
||||
[17] = RCAR_GP_PIN(0, 28), /* DU0_DB1 */
|
||||
[18] = RCAR_GP_PIN(6, 3), /* DU0_DB2 */
|
||||
[19] = RCAR_GP_PIN(6, 4), /* DU0_DB3 */
|
||||
[20] = RCAR_GP_PIN(6, 5), /* DU0_DB4 */
|
||||
[21] = RCAR_GP_PIN(6, 6), /* DU0_DB5 */
|
||||
[22] = RCAR_GP_PIN(6, 7), /* DU0_DB6 */
|
||||
[23] = RCAR_GP_PIN(6, 8), /* DU0_DB7 */
|
||||
[24] = RCAR_GP_PIN(0, 29), /* DU0_DOTCLKIN */
|
||||
[25] = RCAR_GP_PIN(5, 20), /* DU0_DOTCLKOUT0 */
|
||||
[26] = RCAR_GP_PIN(5, 21), /* DU0_HSYNC */
|
||||
[27] = RCAR_GP_PIN(5, 22), /* DU0_VSYNC */
|
||||
[28] = RCAR_GP_PIN(0, 31), /* DU0_EXODDF */
|
||||
[29] = RCAR_GP_PIN(1, 0), /* DU0_DISP */
|
||||
[30] = RCAR_GP_PIN(1, 1), /* DU0_CDE */
|
||||
[31] = RCAR_GP_PIN(0, 30), /* DU0_DOTCLKOUT1 */
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR3", 0xfffc010c, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(1, 2), /* DU1_DR0 */
|
||||
[ 1] = RCAR_GP_PIN(1, 3), /* DU1_DR1 */
|
||||
[ 2] = RCAR_GP_PIN(1, 4), /* DU1_DR2 */
|
||||
[ 3] = RCAR_GP_PIN(1, 5), /* DU1_DR3 */
|
||||
[ 4] = RCAR_GP_PIN(1, 6), /* DU1_DR4 */
|
||||
[ 5] = RCAR_GP_PIN(1, 7), /* DU1_DR5 */
|
||||
[ 6] = RCAR_GP_PIN(1, 8), /* DU1_DR6 */
|
||||
[ 7] = RCAR_GP_PIN(1, 9), /* DU1_DR7 */
|
||||
[ 8] = RCAR_GP_PIN(1, 10), /* DU1_DG0 */
|
||||
[ 9] = RCAR_GP_PIN(1, 11), /* DU1_DG1 */
|
||||
[10] = RCAR_GP_PIN(1, 12), /* DU1_DG2 */
|
||||
[11] = RCAR_GP_PIN(1, 13), /* DU1_DG3 */
|
||||
[12] = RCAR_GP_PIN(1, 14), /* DU1_DG4 */
|
||||
[13] = RCAR_GP_PIN(1, 15), /* DU1_DG5 */
|
||||
[14] = RCAR_GP_PIN(1, 16), /* DU1_DG6 */
|
||||
[15] = RCAR_GP_PIN(1, 17), /* DU1_DG7 */
|
||||
[16] = RCAR_GP_PIN(1, 18), /* DU1_DB0 */
|
||||
[17] = RCAR_GP_PIN(1, 19), /* DU1_DB1 */
|
||||
[18] = RCAR_GP_PIN(1, 20), /* DU1_DB2 */
|
||||
[19] = RCAR_GP_PIN(1, 21), /* DU1_DB3 */
|
||||
[20] = RCAR_GP_PIN(1, 22), /* DU1_DB4 */
|
||||
[21] = RCAR_GP_PIN(1, 23), /* DU1_DB5 */
|
||||
[22] = RCAR_GP_PIN(1, 24), /* DU1_DB6 */
|
||||
[23] = RCAR_GP_PIN(1, 25), /* DU1_DB7 */
|
||||
[24] = RCAR_GP_PIN(1, 26), /* DU1_DOTCLKIN */
|
||||
[25] = RCAR_GP_PIN(1, 27), /* DU1_DOTCLKOUT */
|
||||
[26] = RCAR_GP_PIN(1, 28), /* DU1_HSYNC */
|
||||
[27] = RCAR_GP_PIN(1, 29), /* DU1_VSYNC */
|
||||
[28] = RCAR_GP_PIN(1, 30), /* DU1_EXODDF */
|
||||
[29] = RCAR_GP_PIN(1, 31), /* DU1_DISP */
|
||||
[30] = RCAR_GP_PIN(2, 0), /* DU1_CDE */
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR4", 0xfffc0110, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(2, 30), /* VI1_CLK */
|
||||
[ 1] = SH_PFC_PIN_NONE,
|
||||
[ 2] = SH_PFC_PIN_NONE,
|
||||
[ 3] = RCAR_GP_PIN(2, 31), /* VI1_HSYNC# */
|
||||
[ 4] = RCAR_GP_PIN(3, 0), /* VI1_VSYNC# */
|
||||
[ 5] = RCAR_GP_PIN(3, 1), /* VI1_DATA0 */
|
||||
[ 6] = RCAR_GP_PIN(3, 2), /* VI1_DATA1 */
|
||||
[ 7] = RCAR_GP_PIN(3, 3), /* VI1_DATA2 */
|
||||
[ 8] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */
|
||||
[ 9] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */
|
||||
[10] = RCAR_GP_PIN(3, 6), /* VI1_DATA5 */
|
||||
[11] = RCAR_GP_PIN(3, 7), /* VI1_DATA6 */
|
||||
[12] = RCAR_GP_PIN(3, 8), /* VI1_DATA7 */
|
||||
[13] = RCAR_GP_PIN(3, 9), /* VI1_G0 */
|
||||
[14] = RCAR_GP_PIN(3, 10), /* VI1_G1 */
|
||||
[15] = RCAR_GP_PIN(3, 11), /* VI1_G2 */
|
||||
[16] = RCAR_GP_PIN(3, 12), /* VI1_G3 */
|
||||
[17] = RCAR_GP_PIN(3, 13), /* VI1_G4 */
|
||||
[18] = RCAR_GP_PIN(3, 14), /* VI1_G5 */
|
||||
[19] = RCAR_GP_PIN(3, 15), /* VI1_G6 */
|
||||
[20] = RCAR_GP_PIN(3, 16), /* VI1_G7 */
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR5", 0xfffc0114, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(3, 30), /* SSI_SCK0129 */
|
||||
[ 1] = RCAR_GP_PIN(3, 31), /* SSI_WS0129 */
|
||||
[ 2] = RCAR_GP_PIN(4, 0), /* SSI_SDATA0 */
|
||||
[ 3] = RCAR_GP_PIN(4, 1), /* SSI_SDATA1 */
|
||||
[ 4] = RCAR_GP_PIN(4, 2), /* SSI_SDATA2 */
|
||||
[ 5] = RCAR_GP_PIN(4, 3), /* SSI_SCK34 */
|
||||
[ 6] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */
|
||||
[ 7] = RCAR_GP_PIN(4, 5), /* SSI_SDATA3 */
|
||||
[ 8] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4 */
|
||||
[ 9] = RCAR_GP_PIN(4, 7), /* SSI_SCK5 */
|
||||
[10] = RCAR_GP_PIN(4, 8), /* SSI_WS5 */
|
||||
[11] = RCAR_GP_PIN(4, 9), /* SSI_SDATA5 */
|
||||
[12] = RCAR_GP_PIN(4, 10), /* SSI_SCK6 */
|
||||
[13] = RCAR_GP_PIN(4, 11), /* SSI_WS6 */
|
||||
[14] = RCAR_GP_PIN(4, 12), /* SSI_SDATA6 */
|
||||
[15] = RCAR_GP_PIN(4, 13), /* SSI_SCK78 */
|
||||
[16] = RCAR_GP_PIN(4, 14), /* SSI_WS78 */
|
||||
[17] = RCAR_GP_PIN(4, 15), /* SSI_SDATA7 */
|
||||
[18] = RCAR_GP_PIN(4, 16), /* SSI_SDATA8 */
|
||||
[19] = SH_PFC_PIN_NONE,
|
||||
[20] = RCAR_GP_PIN(3, 17), /* SD0_CLK */
|
||||
[21] = RCAR_GP_PIN(3, 18), /* SD0_CMD */
|
||||
[22] = RCAR_GP_PIN(3, 21), /* SD0_DAT0 */
|
||||
[23] = RCAR_GP_PIN(3, 22), /* SD0_DAT1 */
|
||||
[24] = RCAR_GP_PIN(3, 23), /* SD0_DAT2 */
|
||||
[25] = RCAR_GP_PIN(3, 24), /* SD0_DAT3 */
|
||||
[26] = RCAR_GP_PIN(3, 19), /* SD0_CD */
|
||||
[27] = RCAR_GP_PIN(3, 20), /* SD0_WP */
|
||||
[28] = RCAR_GP_PIN(3, 28), /* AUDIO_CLKA */
|
||||
[29] = RCAR_GP_PIN(3, 29), /* AUDIO_CLKB */
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ PINMUX_BIAS_REG("PUPR6", 0xfffc0118, "N/A", 0) {
|
||||
[ 0] = RCAR_GP_PIN(4, 26), /* PENC0 */
|
||||
[ 1] = RCAR_GP_PIN(4, 27), /* PENC1 */
|
||||
[ 2] = RCAR_GP_PIN(4, 28), /* PENC2 */
|
||||
[ 3] = SH_PFC_PIN_NONE,
|
||||
[ 4] = SH_PFC_PIN_NONE,
|
||||
[ 5] = RCAR_GP_PIN(4, 20), /* HTX0 */
|
||||
[ 6] = RCAR_GP_PIN(4, 21), /* HRX0 */
|
||||
[ 7] = RCAR_GP_PIN(4, 17), /* HSCK0 */
|
||||
[ 8] = RCAR_GP_PIN(4, 18), /* HCTS0# */
|
||||
[ 9] = RCAR_GP_PIN(4, 19), /* HRTS0# */
|
||||
[10] = RCAR_GP_PIN(4, 22), /* HSPI_CLK0 */
|
||||
[11] = RCAR_GP_PIN(4, 23), /* HSPI_CS0# */
|
||||
[12] = RCAR_GP_PIN(4, 24), /* HSPI_TX0 */
|
||||
[13] = RCAR_GP_PIN(4, 25), /* HSPI_RX0 */
|
||||
[14] = RCAR_GP_PIN(4, 29), /* FMCLK */
|
||||
[15] = RCAR_GP_PIN(4, 30), /* BPFCLK */
|
||||
[16] = RCAR_GP_PIN(4, 31), /* FMIN */
|
||||
[17] = RCAR_GP_PIN(0, 12), /* CLKOUT */
|
||||
[18] = RCAR_GP_PIN(0, 13), /* CS0# */
|
||||
[19] = RCAR_GP_PIN(0, 14), /* CS1#/A26 */
|
||||
[20] = RCAR_GP_PIN(5, 16), /* RD# */
|
||||
[21] = SH_PFC_PIN_NONE,
|
||||
[22] = SH_PFC_PIN_NONE,
|
||||
[23] = SH_PFC_PIN_NONE,
|
||||
[24] = SH_PFC_PIN_NONE,
|
||||
[25] = SH_PFC_PIN_NONE,
|
||||
[26] = SH_PFC_PIN_NONE,
|
||||
[27] = SH_PFC_PIN_NONE,
|
||||
[28] = SH_PFC_PIN_NONE,
|
||||
[29] = SH_PFC_PIN_NONE,
|
||||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7779_pfc_ops = {
|
||||
.get_bias = rcar_pinmux_get_bias,
|
||||
.set_bias = rcar_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a7779_pinmux_info = {
|
||||
.name = "r8a7779_pfc",
|
||||
.ops = &r8a7779_pfc_ops,
|
||||
|
||||
.unlock_reg = 0xfffc0000, /* PMMR */
|
||||
|
||||
|
|
@ -3937,6 +4366,7 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
|
|
@ -5824,7 +5824,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* SEL_I2C1 [2] */
|
||||
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
|
|
@ -6552,7 +6552,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
|
||||
/* RESERVED [6] */ ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
|
|
@ -6874,7 +6874,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
|
||||
|
|
|
|||
|
|
@ -2625,7 +2625,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* IP7_1_0 [2] */
|
||||
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
|
|
|
|||
|
|
@ -42,30 +42,30 @@
|
|||
PORT_GP_1(5, 25, fn, sfx), \
|
||||
PORT_GP_1(5, 26, fn, sfx), \
|
||||
PORT_GP_1(5, 27, fn, sfx), \
|
||||
PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
|
||||
|
||||
|
|
@ -5512,7 +5512,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
FN_SEL_SSI9_0, FN_SEL_SSI9_1,
|
||||
/* RESERVED [12] */ ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
|
|
|
|||
|
|
@ -17,12 +17,12 @@
|
|||
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
|
||||
|
|
@ -5610,7 +5610,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* RESERVED 16-1 */
|
||||
MOD_SEL2_0 ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
|
|
@ -5861,7 +5861,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
|
||||
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
|
||||
} },
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
|
|
@ -5872,7 +5872,7 @@ enum ioctrl_regs {
|
|||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[POCCTRL] = { 0xe6060380, },
|
||||
[TDSELCTRL] = { 0xe60603c0, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
|
|
@ -6129,7 +6129,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
|
||||
|
|
|
|||
|
|
@ -22,12 +22,12 @@
|
|||
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
|
||||
|
|
@ -5565,7 +5565,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* RESERVED 16-1 */
|
||||
MOD_SEL2_0 ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
|
|
@ -5813,7 +5813,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
|
||||
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
|
||||
} },
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
|
|
@ -5824,7 +5824,7 @@ enum ioctrl_regs {
|
|||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[POCCTRL] = { 0xe6060380, },
|
||||
[TDSELCTRL] = { 0xe60603c0, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
|
|
@ -6081,7 +6081,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
|
||||
|
|
|
|||
|
|
@ -23,12 +23,12 @@
|
|||
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
|
||||
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
|
||||
|
|
@ -5806,7 +5806,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* RESERVED 16-1 */
|
||||
MOD_SEL2_0 ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
|
|
@ -6054,7 +6054,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
|
||||
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
|
||||
} },
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
|
|
@ -6065,7 +6065,7 @@ enum ioctrl_regs {
|
|||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[POCCTRL] = { 0xe6060380, },
|
||||
[TDSELCTRL] = { 0xe60603c0, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
|
|
@ -6322,7 +6322,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@
|
|||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
|
|
@ -34,7 +34,8 @@
|
|||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
|
|
@ -2342,7 +2343,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_1
|
||||
MOD_SEL0_0 ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
|
|
@ -2357,26 +2358,37 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
[POCCTRL1] = { 0xe6060384 },
|
||||
[POCCTRL2] = { 0xe6060388 },
|
||||
[TDSELCTRL] = { 0xe60603c0, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
|
||||
switch (pin) {
|
||||
case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
return bit;
|
||||
if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
|
||||
|
||||
case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
return bit + 22;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
|
||||
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
|
||||
case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
|
||||
return bit - 10;
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
|
||||
|
||||
case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
|
||||
return bit + 7;
|
||||
|
||||
return -EINVAL;
|
||||
case PIN_VDDQ_AVB0:
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
|
||||
return 0;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@
|
|||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_GP(fn, sfx) \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
||||
|
|
@ -35,7 +35,9 @@
|
|||
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
|
||||
PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
|
|
@ -2813,7 +2815,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL0_1
|
||||
MOD_SEL0_0 ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
|
|
@ -2830,31 +2832,46 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
[POCCTRL2] = { 0xe6060388, },
|
||||
[POCCTRL3] = { 0xe606038c, },
|
||||
[TDSELCTRL] = { 0xe60603c0, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
|
||||
switch (pin) {
|
||||
case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
return bit;
|
||||
else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
|
||||
|
||||
case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
return bit + 22;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
|
||||
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
|
||||
case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
|
||||
return bit - 10;
|
||||
if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
|
||||
(pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
|
||||
|
||||
case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
|
||||
case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
|
||||
return bit + 7;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
|
||||
if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
|
||||
case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
|
||||
return pin - 25;
|
||||
|
||||
return -EINVAL;
|
||||
case PIN_VDDQ_AVB:
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
|
||||
return 0;
|
||||
|
||||
case PIN_VDDQ_GE:
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
|
||||
return 1;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
|
|
|
|||
|
|
@ -22,12 +22,12 @@
|
|||
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
|
|
@ -56,7 +56,8 @@
|
|||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
|
||||
PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
|
|
@ -507,7 +508,8 @@ MOD_SEL0_1_0
|
|||
FM(AVB_TD3) \
|
||||
FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
|
||||
FM(ASEBRK) \
|
||||
FM(MLB_REF)
|
||||
FM(MLB_REF) \
|
||||
FM(VDDQ_AVB0)
|
||||
|
||||
enum {
|
||||
PINMUX_RESERVED = 0,
|
||||
|
|
@ -5002,7 +5004,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_4
|
||||
/* RESERVED 3, 2, 1, 0 */ ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
|
|
@ -5035,33 +5037,40 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */
|
||||
{ RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */
|
||||
} },
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
POCCTRL0,
|
||||
POCCTRL2,
|
||||
TDSELCTRL,
|
||||
};
|
||||
|
||||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[POCCTRL0] = { 0xe6060380, },
|
||||
[POCCTRL2] = { 0xe6060388, },
|
||||
[TDSELCTRL] = { 0xe60603c0, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
switch (pin) {
|
||||
case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 11):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
return pin & 0x1f;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 10):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
return (pin & 0x1f) + 19;
|
||||
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
|
||||
bit = pin & 0x1f;
|
||||
case PIN_VDDQ_AVB0:
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
|
||||
return 0;
|
||||
|
||||
if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
|
||||
bit = (pin & 0x1f) + 19;
|
||||
|
||||
return bit;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
|
|
@ -5269,7 +5278,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */
|
||||
[31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
|
||||
PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
|
||||
|
|
@ -34,7 +34,8 @@
|
|||
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
|
||||
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
|
||||
PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
|
||||
|
||||
/*
|
||||
* F_() : just information
|
||||
|
|
@ -2852,19 +2853,37 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_26
|
||||
/* RESERVED 25-0 */ ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
POCCTRL0,
|
||||
POCCTRL2,
|
||||
TDSELCTRL,
|
||||
};
|
||||
|
||||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[POCCTRL0] = { 0xe6060380, },
|
||||
[POCCTRL2] = { 0xe6060388, },
|
||||
[TDSELCTRL] = { 0xe60603c0, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = -EINVAL;
|
||||
switch (pin) {
|
||||
case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9):
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
|
||||
return 29 - (pin - RCAR_GP_PIN(3, 0));
|
||||
|
||||
*pocctrl = 0xe6060380;
|
||||
case PIN_VDDQ_AVB0:
|
||||
*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
|
||||
return 0;
|
||||
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
|
||||
bit = 29 - (pin - RCAR_GP_PIN(3, 0));
|
||||
|
||||
return bit;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
|
|
@ -3075,15 +3094,6 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
TDSELCTRL,
|
||||
};
|
||||
|
||||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[TDSELCTRL] = { 0xe60603c0, },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const struct pinmux_bias_reg *
|
||||
r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int *puen_bit, unsigned int *pud_bit)
|
||||
|
|
|
|||
|
|
@ -3630,7 +3630,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL2_3_2
|
||||
/* RESERVED 1-0 */ ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
|
|
@ -3935,7 +3935,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
|
||||
{ RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
|
||||
} },
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
|
|
@ -3962,7 +3962,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
[POC8] = { 0xe60690a0, },
|
||||
[POC9] = { 0xe60698a0, },
|
||||
[TD1SEL0] = { 0xe6058124, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
|
|
@ -4349,7 +4349,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
|
||||
|
|
|
|||
|
|
@ -1784,7 +1784,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL1_3_2
|
||||
MOD_SEL1_1_0))
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
|
|
@ -1896,7 +1896,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
|
||||
{ RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
|
|
@ -1911,7 +1911,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
[POC1] = { 0xe60508a0, },
|
||||
[POC3] = { 0xe60518a0, },
|
||||
[TD0SEL1] = { 0xe6050920, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
|
|
@ -2070,7 +2070,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
|
||||
|
|
|
|||
|
|
@ -49,6 +49,12 @@
|
|||
PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
|
||||
PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
|
||||
|
||||
#define CPU_ALL_NOGP(fn) \
|
||||
PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
|
||||
PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
|
||||
PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
|
||||
PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
|
||||
|
||||
/* GPSR0 */
|
||||
#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
|
||||
#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
|
||||
|
|
@ -1221,10 +1227,12 @@ static const u16 pinmux_data[] = {
|
|||
*/
|
||||
enum {
|
||||
GP_ASSIGN_LAST(),
|
||||
NOGP_ALL(),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
PINMUX_GPIO_GP_ALL(),
|
||||
PINMUX_NOGP_ALL(),
|
||||
};
|
||||
|
||||
/* - AUDIO CLOCK ----------------------------------------- */
|
||||
|
|
@ -3681,7 +3689,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MOD_SEL8_1
|
||||
MOD_SEL8_0))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
|
|
@ -3943,7 +3951,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
|||
{ RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
|
||||
{ RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
|
||||
} },
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
|
|
@ -3966,30 +3974,49 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
|||
[POC6] = { 0xE60610A0, },
|
||||
[POC7] = { 0xE60618A0, },
|
||||
[POC8] = { 0xE60680A0, },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POC0].reg;
|
||||
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
|
||||
switch (pin) {
|
||||
case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
|
||||
*pocctrl = pinmux_ioctrl_regs[POC0].reg;
|
||||
return bit;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POC1].reg;
|
||||
if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22))
|
||||
case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
|
||||
*pocctrl = pinmux_ioctrl_regs[POC1].reg;
|
||||
return bit;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POC3].reg;
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
|
||||
case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
|
||||
*pocctrl = pinmux_ioctrl_regs[POC3].reg;
|
||||
return bit;
|
||||
|
||||
*pocctrl = pinmux_ioctrl_regs[POC8].reg;
|
||||
if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
|
||||
case PIN_VDDQ_TSN0:
|
||||
*pocctrl = pinmux_ioctrl_regs[POC4].reg;
|
||||
return 0;
|
||||
|
||||
case PIN_VDDQ_AVB2:
|
||||
*pocctrl = pinmux_ioctrl_regs[POC5].reg;
|
||||
return 0;
|
||||
|
||||
case PIN_VDDQ_AVB1:
|
||||
*pocctrl = pinmux_ioctrl_regs[POC6].reg;
|
||||
return 0;
|
||||
|
||||
case PIN_VDDQ_AVB0:
|
||||
*pocctrl = pinmux_ioctrl_regs[POC7].reg;
|
||||
return 0;
|
||||
|
||||
case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
|
||||
*pocctrl = pinmux_ioctrl_regs[POC8].reg;
|
||||
return bit;
|
||||
|
||||
return -EINVAL;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
|
|
@ -4299,7 +4326,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
|||
[30] = SH_PFC_PIN_NONE,
|
||||
[31] = SH_PFC_PIN_NONE,
|
||||
} },
|
||||
{ /* sentinel */ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a779g0_pin_ops = {
|
||||
|
|
|
|||
|
|
@ -1509,7 +1509,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -1555,7 +1555,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
|
||||
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7203_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -2031,7 +2031,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
PK1_IN, PK1_OUT,
|
||||
PK0_IN, PK0_OUT ))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -2109,7 +2109,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
|
||||
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA ))
|
||||
},
|
||||
{ }
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7264_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -2749,8 +2749,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
PJ1_IN, PJ1_OUT,
|
||||
PJ0_IN, PJ0_OUT ))
|
||||
},
|
||||
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -2828,8 +2827,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA ))
|
||||
},
|
||||
|
||||
{ }
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7269_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -3876,7 +3876,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
/* RESERVED [1] */
|
||||
))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -3980,7 +3980,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
|
||||
PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_irq pinmux_irqs[] = {
|
||||
|
|
|
|||
|
|
@ -1103,7 +1103,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
PTV1_FN, PTV1_OUT, 0, PTV1_IN,
|
||||
PTV0_FN, PTV0_OUT, 0, PTV0_IN ))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -1179,7 +1179,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
0, 0, 0, PTV4_DATA,
|
||||
PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7720_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -1585,7 +1585,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
MSELB8_RGB, MSELB8_SYS,
|
||||
/* RESERVED [8] */ ))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -1681,7 +1681,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
0, 0, PTZ5_DATA, PTZ4_DATA,
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7722_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -1784,7 +1784,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0,
|
||||
PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 ))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -1880,7 +1880,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7723_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -2059,7 +2059,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
PSE1_0, PSE1_1,
|
||||
PSE0_0, PSE0_1))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -2155,7 +2155,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7724_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -2366,7 +2366,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
GP_5_1_IN, GP_5_1_OUT,
|
||||
GP_5_0_IN, GP_5_0_OUT ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -2383,7 +2383,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
|
||||
GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7734_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -2089,7 +2089,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
PS8_8_FN1, PS8_8_FN2,
|
||||
/* RESERVED [8] */ ))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -2197,7 +2197,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
|
||||
PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7757_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -1168,7 +1168,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
P2MSEL1_0, P2MSEL1_1,
|
||||
P2MSEL0_0, P2MSEL0_1 ))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -1236,7 +1236,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
0, 0, 0, 0,
|
||||
PR3_DATA, PR2_DATA, PR1_DATA, PR0_DATA ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7785_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -747,7 +747,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
P2MSEL1_0, P2MSEL1_1,
|
||||
P2MSEL0_0, P2MSEL0_1 ))
|
||||
},
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -787,7 +787,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
|
||||
PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info sh7786_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -502,7 +502,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
|||
PH1_FN, PH1_OUT, PH1_IN, 0,
|
||||
PH0_FN, PH0_OUT, PH0_IN, 0, ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
|
|
@ -538,7 +538,7 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
|||
0, 0, PH5_DATA, PH4_DATA,
|
||||
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, ))
|
||||
},
|
||||
{ },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info shx3_pinmux_info = {
|
||||
|
|
|
|||
|
|
@ -1388,7 +1388,7 @@ static const struct of_device_id rza1_pinctrl_of_match[] = {
|
|||
.compatible = "renesas,r7s72102-ports",
|
||||
.data = &rza1l_pmx_conf,
|
||||
},
|
||||
{ }
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver rza1_pinctrl_driver = {
|
||||
|
|
|
|||
|
|
@ -931,7 +931,7 @@ static int rzn1_pinctrl_remove(struct platform_device *pdev)
|
|||
|
||||
static const struct of_device_id rzn1_pinctrl_match[] = {
|
||||
{ .compatible = "renesas,rzn1-pinctrl", },
|
||||
{}
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
|
||||
|
||||
|
|
|
|||
|
|
@ -559,7 +559,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
|
|||
return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
|
||||
|
||||
case PIN_CONFIG_POWER_SOURCE:
|
||||
return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
|
||||
return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
|
||||
|
||||
default:
|
||||
return false;
|
||||
|
|
@ -612,7 +612,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
|
|||
case PIN_CONFIG_POWER_SOURCE: {
|
||||
int idx = sh_pfc_get_pin_index(pfc, _pin);
|
||||
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
|
||||
unsigned int lower_voltage;
|
||||
unsigned int mode, lo, hi;
|
||||
u32 pocctrl, val;
|
||||
int bit;
|
||||
|
||||
|
|
@ -625,10 +625,11 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
|
|||
|
||||
val = sh_pfc_read(pfc, pocctrl);
|
||||
|
||||
lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
|
||||
2500 : 1800;
|
||||
mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
|
||||
lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
|
||||
hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;
|
||||
|
||||
arg = (val & BIT(bit)) ? 3300 : lower_voltage;
|
||||
arg = (val & BIT(bit)) ? hi : lo;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -684,7 +685,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
|
|||
unsigned int mV = pinconf_to_config_argument(configs[i]);
|
||||
int idx = sh_pfc_get_pin_index(pfc, _pin);
|
||||
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
|
||||
unsigned int lower_voltage;
|
||||
unsigned int mode, lo, hi;
|
||||
u32 pocctrl, val;
|
||||
int bit;
|
||||
|
||||
|
|
@ -695,15 +696,16 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
|
|||
if (WARN(bit < 0, "invalid pin %#x", _pin))
|
||||
return bit;
|
||||
|
||||
lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
|
||||
2500 : 1800;
|
||||
mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
|
||||
lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
|
||||
hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;
|
||||
|
||||
if (mV != lower_voltage && mV != 3300)
|
||||
if (mV != lo && mV != hi)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&pfc->lock, flags);
|
||||
val = sh_pfc_read(pfc, pocctrl);
|
||||
if (mV == 3300)
|
||||
if (mV == hi)
|
||||
val |= BIT(bit);
|
||||
else
|
||||
val &= ~BIT(bit);
|
||||
|
|
|
|||
|
|
@ -29,16 +29,13 @@ enum {
|
|||
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
|
||||
#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
|
||||
SH_PFC_PIN_CFG_PULL_DOWN)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
|
||||
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
|
||||
|
||||
#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
|
||||
#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (1 << 4)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (2 << 4)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (3 << 4)
|
||||
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
|
||||
SH_PFC_PIN_VOLTAGE_18_33)
|
||||
#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
|
||||
SH_PFC_PIN_VOLTAGE_25_33)
|
||||
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 6)
|
||||
|
||||
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user