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UAPI Changes:

Browse Source 
- Use write-back caching mode for system memory on DGFX (Thomas)
 
 Driver Changes:
 - Do not leak object when finalizing hdcp gsc (Nirmoy)
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE6rM8lpABPHM5FqyDm6KlpjDL6lMFAmaQVxwZHGx1Y2FzLmRl
 bWFyY2hpQGludGVsLmNvbQAKCRCboqWmMMvqU9lPEACez8CYyKwO/Gx5AqG5SPti
 SIL/C7GM+lvmOy2HmyJdVwoqGXdlhFRnz2TWpx3gBRAOcUu8deK7SCBW76bok1zD
 rZagw1cYMLcoY9buWL/M4MZX5vRn+pMx2BIBJGHJtwfjN8B2dGL/CQdAqHt6b3yo
 SUMZYWpCzOPpxmcX0M2PCvawPQAzDvepNOUE1FSFMadK5VqZSzu3G96Av0rW5edd
 afNp/cqi7rSwRhTJK5mgW9OVpBXww0xJhx8SySqGefK469eGIH3+eIHm2nuLIqgL
 7bgXNlfkZy7S+ygtiGRZiEOvYnMAOyvQY/QlH9QYuBGRuzjDBD3id0iDi4yGLpw3
 USz2kPj520sNFLS3PVut4CXxxZxSWszdj6wL5/r217yOYPouGkjmDSmkEi5kByni
 a2BsydkcdqL4XIv7LJWg68Mjswjip7VkAmBAk3Z5vuPpCHmsX11cqbhrQHE4JnP4
 07ECY5a0TqCs0CBVxsBzGJhF6YSrd5JRTmclij0P7QAJarhwGsNI/TCzePcoEnky
 T61ntHsqUywqxIj5AHi5SsFPq7uYwkYL4lwsEpuouJAp5IyVygFxOSHTOqQhPny3
 Vd1nvDsD7uZV+m/N2PX23TCcCIAV83AbpAWmvXM3VS60trrwvs4Nzwh04TiedZ4n
 UUxpZmSm/ceds930DeLEKg==
 =byI/
 -----END PGP SIGNATURE-----

Merge tag 'drm-xe-fixes-2024-07-11' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes

UAPI Changes:
- Use write-back caching mode for system memory on DGFX (Thomas)

Driver Changes:
- Do not leak object when finalizing hdcp gsc (Nirmoy)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/vgqz35btnxdddko3byrgww5ii36wig2tvondg2p3j3b3ourj4i@rqgolll3wwkh
This commit is contained in:
Dave Airlie 2024-07-12 13:16:25 +10:00
commit 85e23c6620
4 changed files with 45 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
View File

@ -159,12 +159,16 @@ void intel_hdcp_gsc_fini(struct xe_device *xe)
{
struct intel_hdcp_gsc_message *hdcp_message =
xe->display.hdcp.hdcp_message;
struct i915_hdcp_arbiter *arb = xe->display.hdcp.arbiter;
if (!hdcp_message)
return;
if (hdcp_message) {
xe_bo_unpin_map_no_vm(hdcp_message->hdcp_bo);
kfree(hdcp_message);
xe->display.hdcp.hdcp_message = NULL;
}
xe_bo_unpin_map_no_vm(hdcp_message->hdcp_bo);
kfree(hdcp_message);
kfree(arb);
xe->display.hdcp.arbiter = NULL;
}
static int xe_gsc_send_sync(struct xe_device *xe,

47
drivers/gpu/drm/xe/xe_bo.c
View File

@ -317,7 +317,7 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
struct xe_device *xe = xe_bo_device(bo);
struct xe_ttm_tt *tt;
unsigned long extra_pages;
enum ttm_caching caching;
enum ttm_caching caching = ttm_cached;
int err;
tt = kzalloc(sizeof(*tt), GFP_KERNEL);
@ -331,26 +331,35 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
extra_pages = DIV_ROUND_UP(xe_device_ccs_bytes(xe, bo->size),
PAGE_SIZE);
switch (bo->cpu_caching) {
case DRM_XE_GEM_CPU_CACHING_WC:
caching = ttm_write_combined;
break;
default:
caching = ttm_cached;
break;
}
WARN_ON((bo->flags & XE_BO_FLAG_USER) && !bo->cpu_caching);
/*
* Display scanout is always non-coherent with the CPU cache.
*
* For Xe_LPG and beyond, PPGTT PTE lookups are also non-coherent and
* require a CPU:WC mapping.
* DGFX system memory is always WB / ttm_cached, since
* other caching modes are only supported on x86. DGFX
* GPU system memory accesses are always coherent with the
* CPU.
*/
if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
(xe->info.graphics_verx100 >= 1270 && bo->flags & XE_BO_FLAG_PAGETABLE))
caching = ttm_write_combined;
if (!IS_DGFX(xe)) {
switch (bo->cpu_caching) {
case DRM_XE_GEM_CPU_CACHING_WC:
caching = ttm_write_combined;
break;
default:
caching = ttm_cached;
break;
}
WARN_ON((bo->flags & XE_BO_FLAG_USER) && !bo->cpu_caching);
/*
* Display scanout is always non-coherent with the CPU cache.
*
* For Xe_LPG and beyond, PPGTT PTE lookups are also
* non-coherent and require a CPU:WC mapping.
*/
if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
(xe->info.graphics_verx100 >= 1270 &&
bo->flags & XE_BO_FLAG_PAGETABLE))
caching = ttm_write_combined;
}
err = ttm_tt_init(&tt->ttm, &bo->ttm, page_flags, caching, extra_pages);
if (err) {

3
drivers/gpu/drm/xe/xe_bo_types.h
View File

@ -66,7 +66,8 @@ struct xe_bo {
/**
* @cpu_caching: CPU caching mode. Currently only used for userspace
* objects.
* objects. Exceptions are system memory on DGFX, which is always
* WB.
*/
u16 cpu_caching;

8
include/uapi/drm/xe_drm.h
View File

@ -776,7 +776,13 @@ struct drm_xe_gem_create {
#define DRM_XE_GEM_CPU_CACHING_WC 2
/**
* @cpu_caching: The CPU caching mode to select for this object. If
* mmaping the object the mode selected here will also be used.
* mmaping the object the mode selected here will also be used. The
* exception is when mapping system memory (including data evicted
* to system) on discrete GPUs. The caching mode selected will
* then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency
* between GPU- and CPU is guaranteed. The caching mode of
* existing CPU-mappings will be updated transparently to
* user-space clients.
*/
__u16 cpu_caching;
/** @pad: MBZ */