media: rzg2l-cru: Remove the 'state' variable

The cru driver uses a 'state' variable for debugging purpose in the
interrupt handler. The state is used to detect invalid usage conditions
that are not meant to happen unless the driver has a bug in handling the
stop and start conditions.

Remove the state variable which seems to be a debugging leftover.

Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Jacopo Mondi 2026-02-11 15:27:37 +01:00 committed by Hans Verkuil
parent 145b8d16cc
commit 85d8820d48
2 changed files with 3 additions and 83 deletions

View File

@ -38,20 +38,6 @@ enum rzg2l_csi2_pads {
struct rzg2l_cru_dev;
/**
* enum rzg2l_cru_dma_state - DMA states
* @RZG2L_CRU_DMA_STOPPED: No operation in progress
* @RZG2L_CRU_DMA_STARTING: Capture starting up
* @RZG2L_CRU_DMA_RUNNING: Operation in progress have buffers
* @RZG2L_CRU_DMA_STOPPING: Stopping operation
*/
enum rzg2l_cru_dma_state {
RZG2L_CRU_DMA_STOPPED = 0,
RZG2L_CRU_DMA_STARTING,
RZG2L_CRU_DMA_RUNNING,
RZG2L_CRU_DMA_STOPPING,
};
struct rzg2l_cru_csi {
struct v4l2_async_connection *asd;
struct v4l2_subdev *subdev;
@ -174,7 +160,6 @@ struct rzg2l_cru_dev {
struct vb2_v4l2_buffer *queue_buf[RZG2L_CRU_HW_BUFFER_MAX];
struct list_head buf_list;
unsigned int sequence;
enum rzg2l_cru_dma_state state;
struct v4l2_pix_format format;
};

View File

@ -398,8 +398,6 @@ void rzg2l_cru_stop_image_processing(struct rzg2l_cru_dev *cru)
if (icnms)
dev_err(cru->dev, "Failed stop HW, something is seriously broken\n");
cru->state = RZG2L_CRU_DMA_STOPPED;
/* Wait until the FIFO becomes empty */
for (retries = 5; retries > 0; retries--) {
if (cru->info->fifo_empty(cru))
@ -587,8 +585,6 @@ static int rzg2l_cru_set_stream(struct rzg2l_cru_dev *cru, int on)
static void rzg2l_cru_stop_streaming(struct rzg2l_cru_dev *cru)
{
cru->state = RZG2L_CRU_DMA_STOPPING;
rzg2l_cru_set_stream(cru, 0);
}
@ -600,8 +596,6 @@ irqreturn_t rzg2l_cru_irq(int irq, void *data)
u32 amnmbs;
int slot;
guard(spinlock_irqsave)(&cru->hw_lock);
irq_status = rzg2l_cru_read(cru, CRUnINTS);
if (!irq_status)
return IRQ_RETVAL(handled);
@ -610,20 +604,9 @@ irqreturn_t rzg2l_cru_irq(int irq, void *data)
rzg2l_cru_write(cru, CRUnINTS, rzg2l_cru_read(cru, CRUnINTS));
/* Nothing to do if capture status is 'RZG2L_CRU_DMA_STOPPED' */
if (cru->state == RZG2L_CRU_DMA_STOPPED) {
dev_dbg(cru->dev, "IRQ while state stopped\n");
return IRQ_RETVAL(handled);
}
/* Calculate slot and prepare for new capture. */
guard(spinlock_irqsave)(&cru->hw_lock);
/* Increase stop retries if capture status is 'RZG2L_CRU_DMA_STOPPING' */
if (cru->state == RZG2L_CRU_DMA_STOPPING) {
if (irq_status & CRUnINTS_SFS)
dev_dbg(cru->dev, "IRQ while state stopping\n");
return IRQ_RETVAL(handled);
}
/* Prepare for capture and update state */
amnmbs = rzg2l_cru_read(cru, AMnMBS);
cru->active_slot = amnmbs & AMnMBS_MBSTS;
@ -636,20 +619,6 @@ irqreturn_t rzg2l_cru_irq(int irq, void *data)
else
slot = cru->active_slot - 1;
/*
* To hand buffers back in a known order to userspace start
* to capture first from slot 0.
*/
if (cru->state == RZG2L_CRU_DMA_STARTING) {
if (slot != 0) {
dev_dbg(cru->dev, "Starting sync slot: %d\n", slot);
return IRQ_RETVAL(handled);
}
dev_dbg(cru->dev, "Capture start synced!\n");
cru->state = RZG2L_CRU_DMA_RUNNING;
}
/* Capture frame */
if (cru->queue_buf[slot]) {
cru->queue_buf[slot]->field = cru->format.field;
@ -677,49 +646,18 @@ irqreturn_t rzg3e_cru_irq(int irq, void *data)
u32 irq_status;
int slot;
guard(spinlock)(&cru->hw_lock);
irq_status = rzg2l_cru_read(cru, CRUnINTS2);
if (!irq_status)
return IRQ_NONE;
dev_dbg(cru->dev, "CRUnINTS2 0x%x\n", irq_status);
rzg2l_cru_write(cru, CRUnINTS2, rzg2l_cru_read(cru, CRUnINTS2));
/* Nothing to do if capture status is 'RZG2L_CRU_DMA_STOPPED' */
if (cru->state == RZG2L_CRU_DMA_STOPPED) {
dev_dbg(cru->dev, "IRQ while state stopped\n");
return IRQ_HANDLED;
}
if (cru->state == RZG2L_CRU_DMA_STOPPING) {
if (irq_status & CRUnINTS2_FExS(0) ||
irq_status & CRUnINTS2_FExS(1) ||
irq_status & CRUnINTS2_FExS(2) ||
irq_status & CRUnINTS2_FExS(3))
dev_dbg(cru->dev, "IRQ while state stopping\n");
return IRQ_HANDLED;
}
guard(spinlock)(&cru->hw_lock);
slot = cru->active_slot;
cru->active_slot = rzg2l_cru_slot_next(cru, cru->active_slot);
dev_dbg(cru->dev, "Current written slot: %d\n", slot);
/*
* To hand buffers back in a known order to userspace start
* to capture first from slot 0.
*/
if (cru->state == RZG2L_CRU_DMA_STARTING) {
if (slot != 0) {
dev_dbg(cru->dev, "Starting sync slot: %d\n", slot);
return IRQ_HANDLED;
}
dev_dbg(cru->dev, "Capture start synced!\n");
cru->state = RZG2L_CRU_DMA_RUNNING;
}
/* Capture frame */
if (cru->queue_buf[slot]) {
struct vb2_v4l2_buffer *buf = cru->queue_buf[slot];
@ -788,7 +726,6 @@ static int rzg2l_cru_start_streaming_vq(struct vb2_queue *vq, unsigned int count
goto out;
}
cru->state = RZG2L_CRU_DMA_STARTING;
dev_dbg(cru->dev, "Starting to capture\n");
return 0;
@ -861,8 +798,6 @@ int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru)
spin_lock_init(&cru->hw_lock);
spin_lock_init(&cru->qlock);
cru->state = RZG2L_CRU_DMA_STOPPED;
for (i = 0; i < RZG2L_CRU_HW_BUFFER_MAX; i++)
cru->queue_buf[i] = NULL;