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usb: dwc3: SW WA for USB CV9(TD 9.23) compliance test failure
eUSB2 repeater is unable to block KJKJ pulse during ESE1. This is resulting into eUSB2 PHY and repeater going out of sync and next link up in high speed fails. Fix this issue by performing soft reset of eUSB2 PHY. Change-Id: I9913fe4cab03b344dea0525f7a72282cd743a915 Signed-off-by: Mayank Rana <quic_mrana@quicinc.com>
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@ -3204,6 +3204,19 @@ static void dwc3_msm_update_imem_pid(struct dwc3 *dwc)
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}
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}
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static void mdwc3_usb2_phy_soft_reset(struct dwc3_msm *mdwc)
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{
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u32 val;
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val = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0));
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dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0),
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val | DWC3_GUSB2PHYCFG_PHYSOFTRST);
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udelay(20);
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val = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0));
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val &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0), val);
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}
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void dwc3_msm_notify_event(struct dwc3 *dwc,
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enum dwc3_notify_event event, unsigned int value)
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{
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@ -3234,6 +3247,20 @@ void dwc3_msm_notify_event(struct dwc3 *dwc,
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break;
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case DWC3_CONTROLLER_CONNDONE_EVENT:
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dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n");
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/*
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* SW WA for CV9 RESET DEVICE TEST(TD 9.23) compliance failure.
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* Visit eUSB2 phy driver for more details.
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*/
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WARN_ON(mdwc->hs_phy->flags & PHY_HOST_MODE);
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if (mdwc->use_eusb2_phy &&
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(dwc->gadget->speed >= USB_SPEED_SUPER)) {
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usb_phy_notify_connect(mdwc->hs_phy, dwc->gadget->speed);
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udelay(20);
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/* Perform usb2 phy soft reset as given workaround */
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mdwc3_usb2_phy_soft_reset(mdwc);
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}
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/*
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* Add power event if the dbm indicates coming out of L1 by
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* interrupt
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