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arm64: dts: qcom: sm6375: Add GPUCC and Adreno SMMU

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Add GPUCC and Adreno SMMU nodes in preparation for adding the GPU
itself.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230531-topic-sm6375_gpusmmu-v1-2-860943894c71@linaro.org
This commit is contained in:
Konrad Dybcio 2023-05-31 17:04:24 +02:00 committed by Bjorn Andersson
parent 11a1397bbf
commit 852865530a
1 changed files with 37 additions and 0 deletions
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37
arch/arm64/boot/dts/qcom/sm6375.dtsi
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@ -5,6 +5,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -1258,6 +1259,42 @@ usb_1_dwc3: usb@4e00000 {
};
};
adreno_smmu: iommu@5940000 {
compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2";
reg = <0 0x05940000 0 0x10000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
clock-names = "bus";
power-domains = <&gpucc GPU_CX_GDSC>;
};
gpucc: clock-controller@5990000 {
compatible = "qcom,sm6375-gpucc";
reg = <0 0x05990000 0 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
power-domains = <&rpmpd SM6375_VDDGX>;
required-opps = <&rpmpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
remoteproc_mss: remoteproc@6000000 {
compatible = "qcom,sm6375-mpss-pas";
reg = <0 0x06000000 0 0x4040>;