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drm/amd/display: add dcn42b specific SMU clock table read
[Why] On DCN42B the SMU reports its DpmClocks table in a different layout than DCN42, with extra clock domains. The clk_mgr was parsing it with the DCN42 layout. [How] Add a DCN42B DpmClocks struct and a dcn42b_get_smu_clocks() that allocates and parses the DCN42B layout, reusing the shared dcn42 helpers so DCN42 is untouched. Populate DCF, SOC, DISP, DPP and FCLK levels and the memory pstate table. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gabe Teeger
Alex Deucher
parent
8ba869e852
commit
84beee0dd2
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@ -221,10 +221,6 @@ static void init_clk_states(struct clk_mgr *clk_mgr)
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clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
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}
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/* dcn42b_get_dpm_table_from_smu removed: reuse dcn42_get_dpm_table_from_smu.
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* Function is identical - only uses SMU calls, no hardware register differences.
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*/
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void dcn42b_init_clocks(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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@ -412,6 +408,176 @@ static struct clk_mgr_funcs dcn42b_funcs = {
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.is_smu_present = dcn42_is_smu_present,
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};
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typedef struct {
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uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
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uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
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uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
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uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
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uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];
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uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];
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uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];
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uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
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MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];
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uint8_t NumDcfClkLevelsEnabled;
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uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
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uint8_t NumSocClkLevelsEnabled;
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uint8_t VpeClkLevelsEnabled;
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uint8_t NumMemPstatesEnabled;
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uint8_t NumFclkLevelsEnabled;
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uint8_t Spare1;
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uint8_t Spare2;
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uint8_t Spare3;
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uint8_t Spare4;
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uint8_t Spare5[2];
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uint32_t MinGfxClk;
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uint32_t MaxGfxClk;
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uint32_t Spare6[8];
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uint32_t Spare7[8];
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uint32_t Spare8[8];
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uint32_t Spare9[8];
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} DpmClocks_t_dcn42b;
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struct dcn42b_smu_dpm_clks {
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DpmClocks_t_dcn42b *dpm_clks;
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union large_integer mc_address;
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};
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static void dcn42b_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
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struct dcn42b_smu_dpm_clks *smu_dpm_clks)
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{
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DpmClocks_t_dcn42b *table = smu_dpm_clks->dpm_clks;
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if (!clk_mgr->smu_ver)
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return;
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if (!table || smu_dpm_clks->mc_address.quad_part == 0)
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return;
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memset(table, 0, sizeof(*table));
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dcn42_smu_set_dram_addr_high(clk_mgr,
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smu_dpm_clks->mc_address.high_part);
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dcn42_smu_set_dram_addr_low(clk_mgr,
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smu_dpm_clks->mc_address.low_part);
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dcn42_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
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}
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static void dcn42b_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int)
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{
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struct clk_mgr *clk_mgr_base = &clk_mgr_int->base;
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struct dcn42b_smu_dpm_clks smu_dpm_clks = { 0 };
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DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
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(void)dc_logger;
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smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42b *)dm_helpers_allocate_gpu_mem(
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clk_mgr_base->ctx,
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DC_MEM_ALLOC_TYPE_GART,
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sizeof(DpmClocks_t_dcn42b),
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&smu_dpm_clks.mc_address.quad_part);
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ASSERT(smu_dpm_clks.dpm_clks);
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if (clk_mgr_base->ctx->dc->debug.pstate_enabled && smu_dpm_clks.mc_address.quad_part != 0) {
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int i;
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DpmClocks_t_dcn42b *dpm_clks = smu_dpm_clks.dpm_clks;
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dcn42b_get_dpm_table_from_smu(clk_mgr_int, &smu_dpm_clks);
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DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
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"NumDispClkLevelsEnabled: %d\n"
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"NumSocClkLevelsEnabled: %d\n"
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"VpeClkLevelsEnabled: %d\n"
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"FClkLevelsEnabled: %d\n"
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"NumMemPstatesEnabled: %d\n"
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"MinGfxClk: %d\n"
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"MaxGfxClk: %d\n",
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dpm_clks->NumDcfClkLevelsEnabled,
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dpm_clks->NumDispClkLevelsEnabled,
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dpm_clks->NumSocClkLevelsEnabled,
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dpm_clks->VpeClkLevelsEnabled,
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dpm_clks->NumFclkLevelsEnabled,
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dpm_clks->NumMemPstatesEnabled,
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dpm_clks->MinGfxClk,
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dpm_clks->MaxGfxClk);
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for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++)
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DC_LOG_SMU("dpm_clks->DcfClocks[%d] = %d\n", i, dpm_clks->DcfClocks[i]);
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for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)
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DC_LOG_SMU("dpm_clks->DispClocks[%d] = %d\n", i, dpm_clks->DispClocks[i]);
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for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
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DC_LOG_SMU("dpm_clks->SocClocks[%d] = %d\n", i, dpm_clks->SocClocks[i]);
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for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
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DC_LOG_SMU("dpm_clks->FclkClocks_Freq[%d] = %d\n", i, dpm_clks->FclkClocks_Freq[i]);
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DC_LOG_SMU("dpm_clks->FclkClocks_Voltage[%d] = %d\n", i, dpm_clks->FclkClocks_Voltage[i]);
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}
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for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
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DC_LOG_SMU("dpm_clks->SocVoltage[%d] = %d\n", i, dpm_clks->SocVoltage[i]);
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for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++)
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DC_LOG_SMU("dpm_clks.MemPstateTable[%d].UClk = %d MemClk = %d Voltage = %d\n",
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i, dpm_clks->MemPstateTable[i].UClk, dpm_clks->MemPstateTable[i].MemClk, dpm_clks->MemPstateTable[i].Voltage);
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if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) {
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/* DCFCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
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dpm_clks->DcfClocks,
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dpm_clks->NumDcfClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = dpm_clks->NumDcfClkLevelsEnabled;
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/* SOCCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
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dpm_clks->SocClocks,
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dpm_clks->NumSocClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels = dpm_clks->NumSocClkLevelsEnabled;
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/* DISPCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
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dpm_clks->DispClocks,
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dpm_clks->NumDispClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = dpm_clks->NumDispClkLevelsEnabled;
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/* DPPCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
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dpm_clks->DppClocks,
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dpm_clks->NumDispClkLevelsEnabled);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = dpm_clks->NumDispClkLevelsEnabled;
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/* FCLK */
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dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
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dpm_clks->FclkClocks_Freq,
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NUM_FCLK_DPM_LEVELS);
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels = dpm_clks->NumFclkLevelsEnabled;
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clk_mgr_base->bw_params->clk_table.num_entries = dpm_clks->NumFclkLevelsEnabled;
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/* Memory Pstate table is in reverse order for dcn42. Proper way to map this is for pmfw to provide an fclk indexed uclk key since we consume fclk matched pairs.*/
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ASSERT(dpm_clks->NumMemPstatesEnabled <= NUM_MEM_PSTATE_LEVELS);
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if (dpm_clks->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS)
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dpm_clks->NumMemPstatesEnabled = NUM_MEM_PSTATE_LEVELS;
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for (i = 0; i < dpm_clks->NumDcfClkLevelsEnabled; i++) {
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if (i < dpm_clks->NumMemPstatesEnabled) {
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clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].MemClk;
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clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[i].WckRatio);
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} else {
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clk_mgr_base->bw_params->clk_table.entries[i].memclk_mhz = dpm_clks->MemPstateTable[0].MemClk;
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clk_mgr_base->bw_params->clk_table.entries[i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[0].WckRatio);
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}
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}
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumDcfClkLevelsEnabled;
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/* DTBCLK tied off in DCN42B */
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clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = 0;
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clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 0;
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}
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}
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if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
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dm_helpers_free_gpu_mem(clk_mgr_base->ctx, DC_MEM_ALLOC_TYPE_GART,
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smu_dpm_clks.dpm_clks);
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}
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void dcn42b_clk_mgr_construct(
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struct dc_context *ctx,
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struct clk_mgr_dcn42 *clk_mgr,
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@ -473,11 +639,6 @@ void dcn42b_clk_mgr_construct(
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dcn42b_read_ss_info_from_lut(&clk_mgr->base);
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clk_mgr->base.base.bw_params = &dcn42b_bw_params;
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if (clk_mgr->base.smu_present) {
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dcn42_get_smu_clocks(&clk_mgr->base);
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//overwrite values from dcn42_get_smu_clocks since dtbclk is tied off in DCN42B
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clk_mgr->base.base.bw_params->clk_table.entries[0].dtbclk_mhz = 0;
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clk_mgr->base.base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 0;
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clk_mgr->base.base.clks.ref_dtbclk_khz = 0;
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}
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if (clk_mgr->base.smu_present)
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dcn42b_get_smu_clocks(&clk_mgr->base);
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}
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