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gpio: dwapb: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20250825-gpio-mmio-gpio-conv-v1-9-356b4b1d5110@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Bartosz Golaszewski
parent
4ba2193ce0
commit
84bebb7e7e
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@ -8,6 +8,7 @@
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/generic.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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@ -99,7 +100,7 @@ struct dwapb_gpio_port_irqchip {
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};
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struct dwapb_gpio_port {
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struct gpio_chip gc;
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struct gpio_generic_chip chip;
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struct dwapb_gpio_port_irqchip *pirq;
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struct dwapb_gpio *gpio;
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#ifdef CONFIG_PM_SLEEP
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@ -107,8 +108,12 @@ struct dwapb_gpio_port {
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#endif
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unsigned int idx;
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};
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#define to_dwapb_gpio(_gc) \
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(container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
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static inline struct dwapb_gpio *to_dwapb_gpio(struct gpio_chip *gc)
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{
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return container_of(to_gpio_generic_chip(gc),
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struct dwapb_gpio_port, chip)->gpio;
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}
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struct dwapb_gpio {
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struct device *dev;
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@ -148,19 +153,19 @@ static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
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static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
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{
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struct gpio_chip *gc = &gpio->ports[0].gc;
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void __iomem *reg_base = gpio->regs;
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struct gpio_generic_chip *chip = &gpio->ports[0].chip;
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void __iomem *reg_base = gpio->regs;
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return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
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return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offset));
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}
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static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
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u32 val)
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{
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struct gpio_chip *gc = &gpio->ports[0].gc;
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void __iomem *reg_base = gpio->regs;
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struct gpio_generic_chip *chip = &gpio->ports[0].chip;
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void __iomem *reg_base = gpio->regs;
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gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
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gpio_generic_write_reg(chip, reg_base + gpio_reg_convert(gpio, offset), val);
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}
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static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
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@ -186,7 +191,7 @@ static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
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if (!port)
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return;
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gc = &port->gc;
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gc = &port->chip.gc;
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pol = dwapb_read(gpio, GPIO_INT_POLARITY);
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/* Just read the current value right out of the data register */
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@ -201,13 +206,13 @@ static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
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static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
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{
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struct gpio_chip *gc = &gpio->ports[0].gc;
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struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
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unsigned long irq_status;
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irq_hw_number_t hwirq;
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irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
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for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
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int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
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int gpio_irq = irq_find_mapping(gen_gc->gc.irq.domain, hwirq);
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u32 irq_type = irq_get_trigger_type(gpio_irq);
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generic_handle_irq(gpio_irq);
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@ -237,27 +242,27 @@ static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
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static void dwapb_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
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u32 val = BIT(irqd_to_hwirq(d));
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unsigned long flags;
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(gen_gc);
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dwapb_write(gpio, GPIO_PORTA_EOI, val);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void dwapb_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
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dwapb_write(gpio, GPIO_INTMASK, val);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
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val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
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dwapb_write(gpio, GPIO_INTMASK, val);
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}
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gpiochip_disable_irq(gc, hwirq);
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}
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@ -265,59 +270,61 @@ static void dwapb_irq_mask(struct irq_data *d)
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static void dwapb_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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u32 val;
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gpiochip_enable_irq(gc, hwirq);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(gen_gc);
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val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
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dwapb_write(gpio, GPIO_INTMASK, val);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void dwapb_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(gen_gc);
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val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
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dwapb_write(gpio, GPIO_INTEN, val);
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val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
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dwapb_write(gpio, GPIO_INTMASK, val);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void dwapb_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(gen_gc);
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val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
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dwapb_write(gpio, GPIO_INTMASK, val);
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val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
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dwapb_write(gpio, GPIO_INTEN, val);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
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irq_hw_number_t bit = irqd_to_hwirq(d);
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unsigned long level, polarity, flags;
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unsigned long level, polarity;
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guard(gpio_generic_lock_irqsave)(gen_gc);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
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polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
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@ -352,7 +359,6 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
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if (type != IRQ_TYPE_EDGE_BOTH)
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dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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@ -393,11 +399,12 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
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unsigned offset, unsigned debounce)
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{
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struct dwapb_gpio_port *port = gpiochip_get_data(gc);
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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struct dwapb_gpio *gpio = port->gpio;
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unsigned long flags, val_deb;
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unsigned long val_deb;
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unsigned long mask = BIT(offset);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(gen_gc);
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val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
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if (debounce)
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@ -406,8 +413,6 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
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val_deb &= ~mask;
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dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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@ -445,7 +450,7 @@ static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
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struct dwapb_port_property *pp)
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{
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struct dwapb_gpio_port_irqchip *pirq;
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struct gpio_chip *gc = &port->gc;
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struct gpio_chip *gc = &port->chip.gc;
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struct gpio_irq_chip *girq;
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int err;
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@ -501,6 +506,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
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struct dwapb_port_property *pp,
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unsigned int offs)
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{
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struct gpio_generic_chip_config config;
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struct dwapb_gpio_port *port;
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void __iomem *dat, *set, *dirout;
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int err;
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@ -519,32 +525,39 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
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set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
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dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
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config = (typeof(config)){
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.dev = gpio->dev,
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.sz = 4,
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.dat = dat,
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.set = set,
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.dirout = dirout,
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};
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/* This registers 32 GPIO lines per port */
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err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
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NULL, 0);
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err = gpio_generic_chip_init(&port->chip, &config);
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if (err) {
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dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
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port->idx);
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return err;
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}
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port->gc.fwnode = pp->fwnode;
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port->gc.ngpio = pp->ngpio;
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port->gc.base = pp->gpio_base;
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port->gc.request = gpiochip_generic_request;
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port->gc.free = gpiochip_generic_free;
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port->chip.gc.fwnode = pp->fwnode;
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port->chip.gc.ngpio = pp->ngpio;
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port->chip.gc.base = pp->gpio_base;
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port->chip.gc.request = gpiochip_generic_request;
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port->chip.gc.free = gpiochip_generic_free;
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/* Only port A support debounce */
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if (pp->idx == 0)
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port->gc.set_config = dwapb_gpio_set_config;
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port->chip.gc.set_config = dwapb_gpio_set_config;
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else
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port->gc.set_config = gpiochip_generic_config;
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port->chip.gc.set_config = gpiochip_generic_config;
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/* Only port A can provide interrupts in all configurations of the IP */
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if (pp->idx == 0)
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dwapb_configure_irqs(gpio, port, pp);
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err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
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err = devm_gpiochip_add_data(gpio->dev, &port->chip.gc, port);
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if (err) {
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dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
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port->idx);
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@ -750,38 +763,37 @@ static int dwapb_gpio_probe(struct platform_device *pdev)
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static int dwapb_gpio_suspend(struct device *dev)
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{
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struct dwapb_gpio *gpio = dev_get_drvdata(dev);
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struct gpio_chip *gc = &gpio->ports[0].gc;
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unsigned long flags;
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struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
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int i;
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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for (i = 0; i < gpio->nr_ports; i++) {
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unsigned int offset;
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unsigned int idx = gpio->ports[i].idx;
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struct dwapb_context *ctx = gpio->ports[i].ctx;
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scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
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for (i = 0; i < gpio->nr_ports; i++) {
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unsigned int offset;
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unsigned int idx = gpio->ports[i].idx;
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struct dwapb_context *ctx = gpio->ports[i].ctx;
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offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
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ctx->dir = dwapb_read(gpio, offset);
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offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
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ctx->dir = dwapb_read(gpio, offset);
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offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
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ctx->data = dwapb_read(gpio, offset);
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offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
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ctx->data = dwapb_read(gpio, offset);
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offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
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ctx->ext = dwapb_read(gpio, offset);
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offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
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ctx->ext = dwapb_read(gpio, offset);
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/* Only port A can provide interrupts */
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if (idx == 0) {
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ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
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ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
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ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
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ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
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ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
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/* Only port A can provide interrupts */
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if (idx == 0) {
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ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
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ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
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ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
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ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
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ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
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/* Mask out interrupts */
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dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
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/* Mask out interrupts */
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dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
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}
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}
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}
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
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@ -791,8 +803,8 @@ static int dwapb_gpio_suspend(struct device *dev)
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static int dwapb_gpio_resume(struct device *dev)
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{
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struct dwapb_gpio *gpio = dev_get_drvdata(dev);
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struct gpio_chip *gc = &gpio->ports[0].gc;
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unsigned long flags;
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struct gpio_chip *gc = &gpio->ports[0].chip.gc;
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struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
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int i, err;
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err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
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@ -801,7 +813,8 @@ static int dwapb_gpio_resume(struct device *dev)
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return err;
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}
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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guard(gpio_generic_lock_irqsave)(gen_gc);
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for (i = 0; i < gpio->nr_ports; i++) {
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unsigned int offset;
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unsigned int idx = gpio->ports[i].idx;
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@ -828,7 +841,6 @@ static int dwapb_gpio_resume(struct device *dev)
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dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
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}
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}
|
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user