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ZTE arm64 device tree update for 4.11:

Browse Source 
- Enable cpufreq support for zx296718 by using new operating-points-v2
    bindings, so that it works with the generic cpufreq-dt driver.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJYjW1hAAoJEFBXWFqHsHzOkYUH/RNoyrOb3+KWfy0pczLBj98F
 SmF966hsGNPPKNZ+NFhqWdd1/iT9UzdIax09858HQzvyWSL7LSZNwbkHJU/2McKy
 zFo71IAnMNiNti6USiKVNX0HGx9ndnCChzJBUAcum46fJ7Kt0g8zjfBZfGjRq1cQ
 b3b1sJXt5P9+ebjUhrGXAykkS4zwpTHCdRAwmtKQEhU8Q5ri2+pqMtwvrt8XDfxl
 vFbckTpA0byd60TGvl/HecmafpYhXvOU7QGQaknzOnlH2o5dmwf0/i7Cw0sqyQn7
 JeBopKi7N2S2hN7ZlUYcEQ87FRGdf2u5WbQtcTRiYrZwvUf508hNMxGclMKUHNg=
 =EYrK
 -----END PGP SIGNATURE-----

Merge tag 'zte-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

ZTE arm64 device tree update for 4.11:
 - Enable cpufreq support for zx296718 by using new operating-points-v2
   bindings, so that it works with the generic cpufreq-dt driver.

* tag 'zte-dt64-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: zx: support cpu-freq for zx296718

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-01-29 21:15:52 -08:00
commit 84b4e9f5a8
1 changed files with 39 additions and 0 deletions
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39
arch/arm64/boot/dts/zte/zx296718.dtsi
View File

@ -44,6 +44,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/zx296718-clock.h>
/ {
compatible = "zte,zx296718";
@ -81,6 +82,8 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
@ -88,6 +91,8 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
@ -95,6 +100,8 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
@ -102,6 +109,38 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
operating-points-v2 = <&cluster0_opp>;
};
};
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <500000>;
};
opp@648000000 {
opp-hz = /bits/ 64 <648000000>;
clock-latency-ns = <500000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
clock-latency-ns = <500000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
clock-latency-ns = <500000>;
};
opp@1188000000 {
opp-hz = /bits/ 64 <1188000000>;
clock-latency-ns = <500000>;
};
};