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dt-bindings: pinctrl: qcom,glymur-tlmm: Document Mahua TLMM block

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Document the pinctrl compatible for the Mahua SoC, a 12-core variant
of Glymur. The PDC wake IRQ map differs since PDC handles the interrupt
for GPIO 155 instead of GPIO 143 as seen on Glymur.

Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Gopikrishna Garmidi 2026-01-20 09:22:50 -08:00 committed by Linus Walleij
parent 450e2487d5
commit 84a3bc3373
1 changed files with 4 additions and 2 deletions
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6
Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml
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@ -10,14 +10,16 @@ maintainers:
- Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC.
Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,glymur-tlmm
enum:
- qcom,glymur-tlmm
- qcom,mahua-tlmm
reg:
maxItems: 1