From 846938fd046c1ca3083ededaa0ecfcaa88ec2a41 Mon Sep 17 00:00:00 2001 From: Le Ma Date: Tue, 12 May 2026 21:50:24 +0800 Subject: [PATCH] drm/amdgpu: add NPS2 memory cap for soc v1.0 DPX mode DPX currently advertises only NPS1 as a compatible memory partition mode in soc_v1_0_get_xcp_res_info(). As a result, supported_nps_configs and amd-smi partition --accelerator report NPS1 for the DPX profile even when the device supports both NPS1 and NPS2. Include NPS2 in the DPX compatible NPS mask so the reported profile capabilities match the supported memory partition modes. Signed-off-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index fb3c7cb35099..ada99210479f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -963,7 +963,8 @@ static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, break; case AMDGPU_DPX_PARTITION_MODE: num_xcp = 2; - nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | + BIT(AMDGPU_NPS2_PARTITION_MODE); break; case AMDGPU_TPX_PARTITION_MODE: num_xcp = 3;